Principal DFT Engineer

ARM • San Jose, CA

41d

About The Position

Arm's Solutions group DFT team implements DFT for SOC for client, datacenter, automotive, and IOT line of business using the latest DFT and process technologies. We closely collaborate with Arm's partners and internal RTL, Verification, Physical Implementation, and Test engineering teams throughout the life cycle of a project, from an early investigation stage all the way through tape-out and silicon test/characterization on ATE. We are currently hiring across three locations: San Jose, Austin, and San Diego.

Requirements

• This role is for a Principal DFT Architect with 12+ years of confirmed experience in Design for Test
• proven experience handing DFT architecture for complex SOCs in leading technology nodes.
• Core DFT skills considered crucial for this position should include some of the following: Siemens DFT tools, Streaming Scan Network (SSN), Scan compression and insertion, Memory BIST and repair scheme implementation, Logic BIST, JTAG/IJTAG, at-speed test, ATPG, fault simulation, DFT mode timing constraints, back-annotated gate level verification, silicon debug, memory and scan diagnostics.
• Experience with 2.5D and 3D test
• Experience coding Verilog RTL, TCL and/or Perl.

Nice To Haves

• Familiarity with SoC style architectures including multi-clock domain and low power design practices.
• Familiarity with Arm IP like the following: Cortex CPUs, Mali GPUs, AMBA protocols, CoreLink interconnects, CoreSight debug
• Background in high performance design, implementation and timing convergence is a plus
• Experience in leading datacenter SOCs is a plus.
• Experience with Cadence, and/or Synopsys DFT and simulation tools
• Ability to work both collaboratively on a team and independently.
• Innovative and a passion for progress
• Hard-working and excellent time management skills with an ability to multi-task
• An upbeat approach to working on ambitious projects on the cutting edge of technology
• Communicate effectively across teams and sites in different geographies and time zones

Responsibilities

• Architect DFT solutions for SOC catering to multiple line of business
• Coordinates DFT requirements across SOC, IP and product teams.
• Implement, and validate innovative DFT techniques on SOCs and sub-systems.
• Insert DFT logic into SoC as well as sub-system level and validate all DFT features using industry standard simulation tools.
• Work closely with multi-functional teams to support DFT RTL level insertion, synthesis and scan insertion, place-and-route, and static-timing-analysis and timing closure.
• Participate in ATE targeted test patterns, validation and silicon- debug
• Work closely Test and product engineering teams on silicon characterization and validation.

What This Job Offers

• Job Type: Full-time
• Career Level: Senior
• Industry: Professional, Scientific, and Technical Services
• Education Level: No Education Listed
• Number of Employees: 5,001-10,000 employees