DFT Quality Engineer

Broadcom • San Jose, CA

9d

About The Position

Broadcom's ASIC Product Division is seeking candidates for a DFT Quality Engineer position at our San Jose design center in CA. In this role, you will play a crucial part in ensuring the Quality, Yield & Test Costs in our products through Research & Development of comprehensive Design for Test (DFT) structures, patterns & test strategies. You will work collaboratively with cross-functional teams & customers to develop, implement, and validate DFT methodologies, guaranteeing that our products meet the highest quality standards.

Requirements

• Strong DFT background (such as Analog DFT, MBIST, IEEE1687 and others)
• Proven experience in DFT implementation & verification
• Understanding of DFT methodologies, including scan, BIST, and ATPG.
• Proficiency in simulation tools and scripting languages (e.g., Perl, Python, TCL and ruby).
• Strong communication and teamwork abilities.
• The ability to work in a multi-disciplined, cross-functional worldwide team environment.
• Solid knowledge in analog and digital circuit design, and device physics fundamentals.
• Excellent problem solving, debug , root cause analysis and communication skills.
• Experience working on ATE is a plus.
• Bachelors in Electrical/Electronic/Computer Engineering and 15+ years of relevant industry experience or Masters Degree in Electrical/Electronic/Computer Engineering and 13+ years of relevant industry experience

Responsibilities

• Collaborate with Key HPC/AI customers -- driving test, quality and reliability (in-field) improvements
• DPM improvements both at Time0 tests -- and in-field failures (e.g., Silent Data Corruption failures)
• Develop/drive improvements using the RMA process. (including ATE characterization, fault diagnosis, etc.)
• Drive production test improvements for quality & test cost/test time (including data collection & analysis)
• Drive best methods into production. fault models test conditions optimized test content across test steps wafer test, final test and SLT.
• Collaborate with customers on board, system, in-field results to improve chip/ATE/SLT testing.
• data analytics for test/yield optimization (outlier analysis, etc)
• Ensure Broadcom ASIC Product Division understands the test industry -- test trends (e.g., SLT), best methods, DFT/fault models drive improvements using emerging industry methods. (including collaboration with Broadcom's EDA partners)
• Represent Broadcom as an industry leader -- c ollaborate with HPC/AI customers, EDA companies and industry peers
• Cross functional collaboration with Test Engineering, Global Operations on yield/data analytics and Design Integration and IP developers
• Good knowledge of Hierarchical Integration (MCMs, 2.5D/3D)
• General understanding of DFT methods -- collaborate with DFT engineers working on leading edge products
• Collaborate with design and architecture teams to identify and define critical testability requirements.
• Document new learnings, processes, results, and best practices to enhance team knowledge and efficiency.
• Stay updated with the latest trends and technologies in DFT to drive innovation within the team.
• Assisting with silicon failure analysis, diagnostics & yield improvement efforts.
• Interfacing with the customers, physical design and test engineering/manufacturing teams spanning multiple geographies.
• Working closely with IP DFT engineers & other stakeholders.

Benefits

• Medical, dental and vision plans
• 401(K) participation including company matching
• Employee Stock Purchase Program (ESPP)
• Employee Assistance Program (EAP)
• company paid holidays
• paid sick leave and vacation time
• The company follows all applicable laws for Paid Family Leave and other leaves of absence.

What This Job Offers

• Job Type: Full-time
• Career Level: Mid Level
• Number of Employees: 5,001-10,000 employees