Principal ASIC Design Engineer

BLUE ORIGIN • Los Angeles, CA

1d

About The Position

At Blue Origin, we envision millions of people living and working in space for the benefit of Earth. We’re working to develop reusable, safe, and low-cost space vehicles and systems within a culture of safety, collaboration, and inclusion. Join our team of problem solvers as we add new chapters to the history of spaceflight! - The Principal ASIC Design Engineer serves as a technical authority for the design of advanced ASICs enabling Space based communication systems. This role is responsible for crafting architecture, guiding implementation strategy, and driving critical technical decisions across one or more silicon programs.

Requirements

• BS, MS, or PhD in Electrical Engineering, Computer Engineering, or related field.
• 12+ years of ASIC design experience, including ownership of complex chips or multiple tape-outs.
• Expert-level knowledge of digital design, microarchitecture, and full-chip tradeoffs.
• Proven success leading technically exciting silicon programs.
• Strong understanding of communication signal-processing hardware and system integration.
• Ability to influence across organizations and communicate complex technical topics clearly.

Nice To Haves

• Deep expertise in Space based communications, digital modems, phased arrays, or payload processing.
• Experience in advanced FEC architectures, timing recovery, carrier recovery, or channel adaptation hardware.
• Familiarity with rad-hard, fault-tolerant, or high-availability digital design techniques.
• Experience guiding architecture across both commercial and mission-critical applications.
• Strong record of innovation, patents, publications, or major product launches.

Responsibilities

• Define top-level or cross-subsystem digital architecture for Space based communication ASICs and SoCs.
• Lead hardware realization of key communication functions such as modem pipelines, coding engines, digital beamforming, switching fabrics, and packet/data processing.
• Drive end-to-end technical planning from concept through silicon validation.
• Establish system-level tradeoffs among throughput, latency, power, die area, reliability, and manufacturability.
• Provide technical leadership across design, verification, physical design, firmware, packaging, and system teams.
• Review and influence architectural partitioning between ASIC, FPGA, software, and RF/analog domains.
• Develop methodologies and reusable IP strategies that improve schedule, quality, and scalability.
• Mentor technical leaders and act as a go-to expert for critical design reviews and issue resolution.
• Support roadmap planning and future product definition.

Benefits

• Medical, dental, vision, basic and supplemental life insurance, paid parental leave, short and long-term disability, 401(k) with a company match of up to 5%, and an Education Support Program.
• Paid Time Off: Up to four (4) weeks per year based on weekly scheduled hours, and up to 14 company-paid holidays.
• Dependent on role type and job level, employees may be eligible for benefits and bonuses based on the company's intent to reward individual contributions and enable them to share in the company's results, or other factors at the company's sole discretion.
• Bonus amounts and eligibility are not guaranteed and subject to change and cancellation.
• Please check with your recruiter for more details.

What This Job Offers

• Job Type: Full-time
• Career Level: Principal
• Education Level: Ph.D. or professional degree