Principal ASIC Design Engineer

Chelsea Search Group • Irvine, CA

7h

About The Position

Senior or Principal ASIC Design Engineer Key Responsibilities: Design and implement digital circuits using HDL (Verilog/ System Verilog) Perform synthesis, timing analysis, Lint, formal equivalence, Clock Domain Crossing (CDC) analysis Optimize designs for performance, power, and area (PPA) requirements Perform RTL simulation and verification to ensure design functionality Participate in design reviews and provide technical guidance to team members Collaborate with cross-functional teams on system integration and validation Qualifications: Bachelor’s or higher degree in Electrical Engineering, Computer Engineering, or a related field 10+ years of experience in digital design and verification Proficiency in HDLs such as Verilog, or System Verilog Strong understanding of digital design principles and methodologies Familiarity with ASIC design flow, and experience with ASIC design tools Knowledge of low-power design techniques Familiarity with verification methodologies (e.g., UVM, formal verification) Excellent problem-solving, strong communication and teamwork skills Preferred Skills: Strong knowledge of Digital Signal Processing (DSP), Digital Communication, and Forward Error Correction (FEC) techniques Experience with scripting languages (e.g., Python, Tcl) Understanding of Optical Communication Standards is a plus Ability to multitask and adapt to a fast-paced, dynamic environment

Requirements

• Bachelor’s or higher degree in Electrical Engineering, Computer Engineering, or a related field
• 10+ years of experience in digital design and verification
• Proficiency in HDLs such as Verilog, or System Verilog
• Strong understanding of digital design principles and methodologies
• Familiarity with ASIC design flow, and experience with ASIC design tools
• Knowledge of low-power design techniques
• Familiarity with verification methodologies (e.g., UVM, formal verification)
• Excellent problem-solving, strong communication and teamwork skills

Nice To Haves

• Strong knowledge of Digital Signal Processing (DSP), Digital Communication, and Forward Error Correction (FEC) techniques
• Experience with scripting languages (e.g., Python, Tcl)
• Understanding of Optical Communication Standards is a plus
• Ability to multitask and adapt to a fast-paced, dynamic environment

Responsibilities

• Design and implement digital circuits using HDL (Verilog/ System Verilog)
• Perform synthesis, timing analysis, Lint, formal equivalence, Clock Domain Crossing (CDC) analysis
• Optimize designs for performance, power, and area (PPA) requirements
• Perform RTL simulation and verification to ensure design functionality
• Participate in design reviews and provide technical guidance to team members
• Collaborate with cross-functional teams on system integration and validation

What This Job Offers

• Job Type: Full-time
• Career Level: Senior