Principal Advanced Packaging Design Engineer

Marvell•Burlington, VT

32d

About The Position

Marvell's semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities. At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. Your Team, Your Impact The Marvell Advanced Packaging team is responsible for package design and technology development to meet the electrical, mechanical, thermal and system requirements for the next generation high performance computing (HPC), Artificial Intelligence (AI) and networking solutions. The group focuses on signal integrity, power integrity, thermal integrity, mechanical integrity, processability, manufacturability, and reliability, involving high speed signaling and complex power delivery networks (PDNs) requiring innovative and custom solutions to meet constantly evolving customer needs. Many of the new designs require multi-chip, multiple component configurations involving, but not limited to, 2.5D and 3D packages, Co-packaged copper or optics and advanced substrates. Marvell has partnered with the world's leading manufacturers to solve our customer's most challenging designs and integrations with industry-leading packaging technologies. What You Can Expect This engineer will be responsible for leading small project teams of design and simulation engineers to deliver innovative high quality packaging solutions. The engineer will also interface with package suppliers to select package technology to ensure manufacturability, and compliance with performance, reliability, and cost requirements.

Requirements

Extensive experience in substrate and/or board design for advanced package technologies with basic understanding of design for manufacturing and reliability as well as electrical performance and the ability to make trade off decisions accordingly
Proven ability to lead complex package architecture development projects involving all relevant internal and external customer stakeholders
Mastery in tools and workflows: Cadence 3DIC/ISP/APD/SiP
Bachelor's degree in electrical engineering or related fields and 15+ years of related professional experience or master's degree and 12+ years of related professional experience or PhD degree with 8+ years of experience.
Innovative thinking, fundamental understanding of design rules, breakout, place and route, signal shielding, reference plane, power distribution, pinout considering overall package and system requirements.
Experience with current generation HBM, DDR, SerDes, D2D, D2H, ADC, DAC, PCIE, Ethernet, etc
Good understanding of signal and power integrity at substrates, board, package, and system level.
Understanding of advanced 2.5D/3D package technology including (a) CoWoS-S/R/L, (b) EMIB, (c) CPO, (d) CPC
Familiarity in tools and workflows: Cadence Sigrity/Clarity/Innovus/Virtuoso, Ansys, AutoCAD, SolidWorks
Experience contributing to tool, process, and flow development, library maintenance
Experience interacting with chip design and electrical simulation teams to optimize the design. Familiarity with running and interpreting signal and power simulations is a plus
Ability to manage programs involving cross-functional teams. Strong interpersonal skills and willingness to learn new things are necessary along with the ability to work with stakeholders in multiple time zones across the globe.
Strong communication, presentation and documentation skills

Responsibilities

leading small project teams of design and simulation engineers to deliver innovative high quality packaging solutions
interface with package suppliers to select package technology to ensure manufacturability, and compliance with performance, reliability, and cost requirements