Prin SOC Architect

Amazon • San Diego, CA

1d • Onsite

About The Position

The Principal SoC architect is responsible for architecting the 1P SoC and its building blocks based on use case requirements provided by the system architecture team and the definition of the silicon provided by the Device Product Manager (PM). The SOC architect collaborates with the IP architects, the silicon design team and the silicon PM when deciding on the silicon architecture, to deliver the performance/power requirements (input from the system architect), different IP requirements and constraints (input from the IP architect) and area/cost/schedule (input from the Device PM and silicon design team). The SoC Architect is also the Chip Lead for the SoC working closely with Physical Design team to partition the silicon, design the interconnect based on BW and performance requirements and develop preliminary floor plan, clocking and power management based on estimates. During post silicon phase, the SoC architect is the first line of defense for issues arising from ATE or bugs identified from silicon validation. In depth knowledge of test, debug and manufacturability is a must as the principal SoC Architect will help tackle design marginality issues due to process variations and recommend voltage, temperature tradeoffs to improve yield and ensuring that the recommendations are within design specifications. The role also requires deep understanding not only of the SoC micro-architecture but also of all highspeed interfaces (DDR, USB, HDMI etc.) and is expected to provide guidance to the respective domain owners during development and debug. Key deliverable from the SOC architect is the SoC architecture spec, along with the sub-system architecture specs in collaboration with IP architects and design leads. The work of a SOC Architect at Lab126 spans the full chip development lifecycle—from defining specifications for new edge AI-powered multimedia SOCs to reviewing microarchitecture designs and testplans with cross-functional teams. On any given day, you might be crafting architectural specs for an upcoming chip or debugging complex issues with older SOCs during bring-up and validation, requiring seamless collaboration across product, design, verification, and validation teams.

Requirements

• Master's degree in EE or related field
• 10+ years of experience in SoCs and/or silicon development
• 2+ years of experience in the domain listed above
• 2+ years of experience in RTL design, synthesis and timing closure
• 2+ years of DFx (Design for cost, test, manufacturing)

Nice To Haves

• PhD in Electronic Engineering or related field
• Experience leading an SoC project as a lead architect from conception to launch
• Experience in all aspects of SoC design, including front-end architecture development, RTL design and synthesis, RTL modeling and verification, power and performance, and manufacturing and qualification
• Experience designing SoC interconnects for high throughput media blocks and CPUs
• Experience with ARM and x86 ISA
• Expertise in at least one of the following areas: video system architecture, audio DSPs, low power WiFi and BT, graphics and display engines
• Familiarity with silicon manufacturing process, including silicon qualification
• Familiarity with embedded software development and debugging

Responsibilities

• Architecting the 1P SoC and its building blocks based on use case requirements provided by the system architecture team and the definition of the silicon provided by the Device Product Manager (PM)
• Collaborating with the IP architects, the silicon design team and the silicon PM when deciding on the silicon architecture
• Delivering the performance/power requirements (input from the system architect), different IP requirements and constraints (input from the IP architect) and area/cost/schedule (input from the Device PM and silicon design team)
• Acting as the Chip Lead for the SoC working closely with Physical Design team
• Partitioning the silicon
• Designing the interconnect based on BW and performance requirements
• Developing preliminary floor plan, clocking and power management based on estimates
• Serving as the first line of defense for issues arising from ATE or bugs identified from silicon validation during post silicon phase
• Helping tackle design marginality issues due to process variations
• Recommending voltage, temperature tradeoffs to improve yield and ensuring that the recommendations are within design specifications
• Providing guidance to the respective domain owners during development and debug of all highspeed interfaces (DDR, USB, HDMI etc.)
• Delivering the SoC architecture spec, along with the sub-system architecture specs in collaboration with IP architects and design leads
• Defining specifications for new edge AI-powered multimedia SOCs
• Reviewing microarchitecture designs and testplans with cross-functional teams
• Crafting architectural specs for an upcoming chip
• Debugging complex issues with older SOCs during bring-up and validation

Benefits

• sign-on payments
• restricted stock units (RSUs)
• health insurance (medical, dental, vision, prescription, Basic Life & AD&D insurance and option for Supplemental life plans, EAP, Mental Health Support, Medical Advice Line, Flexible Spending Accounts, Adoption and Surrogacy Reimbursement coverage)
• 401(k) matching
• paid time off
• parental leave

What This Job Offers

• Job Type: Full-time
• Career Level: Principal