Product SoC Architect

Intel Corporation•Santa Clara, CA

1d•Hybrid

About The Position

Join our team as a Senior IPU SoC Architect and drive the architectural vision for cutting-edge Infrastructure Processing Unit (IPU) and Data Processing Unit (DPU) platforms. In this strategic role, you'll define compute, memory, and coherency architectures while ensuring optimal end-to-end performance for next-generation data center solutions. You'll be instrumental in shaping architectural decisions that directly impact product scalability, performance efficiency, power optimization, and programmability at hyperscale deployments. As a technical leader, you'll establish performance benchmarks, guide cross-functional validation efforts, and collaborate with diverse engineering teams to identify system bottlenecks and architect innovative solutions. Your expertise in networking and x86 compute architectures will be crucial in positioning our products for market leadership. This is a high-impact role where you'll influence multi-generational architecture roadmaps, drive company-wide technical decisions, and establish yourself as a recognized authority in the field.

Requirements

Batchelor’s degree in Electrical Engineering, Computer Engineering, or in a STEM related Field of Study
8+ years of SoC, CPU, or subsystem architecture experience with proven leadership in compute and/or memory system design
8+ years of experience in networking performance engineering, systems performance optimization, or SoC/IPU/DPU architecture roles
Experience in high-speed Ethernet, packet processing, and data center networking technologies
Experience defining and executing performance workload methodologies, KPI-driven validation processes, analyzing complex performance data, identify root causes, and architect effective solutions

Nice To Haves

Post Graduate degree in Electrical Engineering, Computer Engineering, or in a STEM related Field of Study
ARM/x86 compute and memory subsystem experience, including NUMA systems, cache coherency, or largescale platform architectures
Experience with IPU / SmartNIC or accelerator centric SoCs, particularly in cloud and hyperscale environments
Familiarity with PCIe, CXL, and memory semantics for high performance IO
Experience with performance modeling Techniques (e.g. analytical modeling, simulation, emulation, profiling, and microbenchmarking)
Track record of multi generation architectural ownership and mentoring other architects

Responsibilities

Lead comprehensive architecture development for IPU SoCs from initial concept through silicon implementation and post-silicon optimization
Define multi-generation SoC architecture strategy, including processor selection, cache hierarchies, coherency models, and performance/power optimization
Architect scalable coherent mesh and interconnect fabrics, optimizing for latency, bandwidth, scalability, and area efficiency across heterogeneous IPU components
Design advanced system memory architectures incorporating DDR/HBM technologies, memory controllers, cache coherency protocols, bandwidth allocation, QoS management, and isolation mechanisms
Drive SMMU/IOMMU architecture for virtualization-intensive IPU workloads, addressing address translation, ATS/PRI protocols, security boundaries, and multi-tenant isolation
Convert complex cloud, networking, storage, security, and virtualization requirements into actionable architectural specifications and design targets
Conduct comprehensive architecture studies balancing performance, power consumption, silicon area, cost implications, and software compatibility
Establish representative, scalable performance benchmarks for IPU/DPU applications including cloud networking offloads, service chaining, storage acceleration, security processing, virtualization, telemetry, and control-plane operations
Transform product requirements into measurable performance indicators and success metrics
Create comprehensive workload testing frameworks covering steady-state operations, burst scenarios, microbenchmarks, and end-to-end system validation, including stress testing and edge cases
Develop and maintain performance specifications, acceptance criteria, and release gate metrics
Provide technical guidance across silicon design, firmware development, operating system integration, driver development, and system architecture teams
Lead complex performance analysis initiatives, identify root causes of bottlenecks, and propose architectural solutions to meet product objectives
Ability to work autonomously while driving alignment across multiple engineering teams
Strong communication and influence capabilities with experience driving architectural consensus among diverse stakeholders