Power Architect

OpenAI • San Francisco, CA

2d

About The Position

We are seeking a highly skilled cross-stack power architect with deep expertise in making ML systems energy efficient. This hands-on individual contributor will sit within our silicon implementation team and work closely with architecture, kernels, chip design, silicon implementation, platform design, and the broader industry ecosystem to architect, implement, and deploy performance-per-watt optimized next-generation AI accelerator chips and systems.

Requirements

• Relevant degree and strong industry experience focused on the end-to-end energy-efficient ML silicon codesign
• Hands-on experience with power architecture, power estimation, power management and power optimization is required.
• Fundamental understanding of ML chip and platform architecture, performance modeling and workload power/performance characteristics is strongly preferred.
• Hands-on experience with power bring-up and power validation is strongly preferred.

Responsibilities

• Oversee power architecture, implementation, and execution in silicon from concept to high-volume deployment, and propose high-ROI features to maximize performance under power envelope
• Build chip and system-level power models grounded in empirical data and experience to guide organization-wide energy efficiency strategy. This requires a detailed understanding of ML workloads, ML chip and system architecture, silicon design, implementation, and characterization
• Collaborate with chip and platform architecture/design teams to explore and implement power management features, including the specification and implementation of digital/mixed-signal IP, sensing and telemetry, firmware/system software, and silicon characterization methodology (in partnership with engineering teams)
• Partner with silicon design and implementation teams, to optimize performance under power envelope. This includes (but is not limited to) clocking and power domain architecture, voltage/frequency selection, microarchitecture and physical-design driven power reduction, post-silicon voltage margin optimization and workload-informed power optimization
• Work with ecosystem partners (EDA, ASIC, IP, component vendors) to drive innovations that can improve energy efficiency

What This Job Offers

• Job Type: Full-time
• Career Level: Mid Level
• Education Level: No Education Listed
• Number of Employees: 1,001-5,000 employees