Physical Design Engineer (7452)

TSMC • San Jose, CA

10d

About The Position

Are you a highly motivated and skilled Physical Design Engineer with at least 3 years of industrial experience eager to push the boundaries of semiconductor technology? Join our dynamic Test Chip Physical Implementation team in San Jose, CA, and play a critical role in bringing TSMC’s most advanced process nodes (A16/A14/A10) to life. This is an exciting opportunity for an engineer with a strong foundation in VLSI design, a passion for innovation, and hands-on experience with cutting-edge EDA tools. You will be instrumental in the physical implementation and tapeout of complex test vehicles, contributing directly to the future of high-performance computing and advanced electronics.

Requirements

• Master’s Degree or higher in Electrical Engineering or Computer Science, with a strong academic background in VLSI-related coursework and projects.
• A minimum of 3 years of industrial experience in physical design or a closely related field within the semiconductor industry.
• Demonstrated expertise in digital circuit concepts and a deep understanding of the full physical design implementation flow (auto placement and route, STA, layout design, physical verification, IREM signoff).
• Hands-on experience with major EDA tools from Synopsys (e.g., ICC2, DC, Primetime, StarRC, ICV) and Cadence (e.g., Innovus, Virtuoso, SimVision).
• Proficiency in scripting languages such as Python, TCL, CSH, Verilog, and Unix shell scripting.
• Strong analytical and problem-solving skills with meticulous attention to detail.
• Excellent written and verbal communication skills, with the ability to articulate complex technical concepts clearly.
• Positive, collaborative, self-motivated, and adaptable team player capable of thriving in a fast-paced, diverse cultural environment.

Nice To Haves

• Prior internship or professional experience in physical design, circuit design, or related semiconductor roles.
• Experience in optimizing placement strategies, congestion removal, and post-placement timing closure.
• Familiarity with clock tree synthesis techniques to mitigate latency and skew.
• Knowledge of Power Integrity (PI) and Signal Integrity (SI) closure techniques.
• Experience with multi-voltage design concepts and low-power techniques.
• Familiarity with other EDA tools such as Ansys Redhawk or Synopsys Fusion Compiler.
• DFT knowledge is a plus.

Responsibilities

• Drive the end-to-end physical implementation and tapeout of test vehicles on TSMC’s leading-edge process nodes (A16/A14/A10).
• Execute comprehensive physical design flows from netlist-to-GDS, including: Block and SoC-level floorplanning, power grid implementation, and low-power structure integration.
• Advanced placement, clock tree synthesis (CTS), and routing for optimal performance and congestion management.
• Extensive design optimization for power, performance, and area (PPA) targets.
• Perform rigorous design signoff verification, encompassing: RC extraction, Static Timing Analysis (STA), IR/EM analysis (IREM), Design Rule Check (DRC), Layout Versus Schematic (LVS), Electrical Rule Check (ERC), and Voltage-Aware Layout Parasitic (VCLP) analysis.
• Achieve robust timing closure, physical design closure, and power/signal integrity closure based on comprehensive signoff verification results.
• Actively contribute to the development and evaluation of advanced methodologies and flows to meet aggressive PPA goals.
• Develop and enhance CAD automation scripts and dashboards using TCL, Python, CSH, and other scripting languages to streamline design flows and ensure quality monitoring.
• Collaborate effectively with cross-functional teams, including RTL, DFT, and CAD, to provide insightful feedback and ensure seamless integration throughout the design cycle.

What This Job Offers

• Job Type: Full-time
• Career Level: Mid Level