Package Design Engineer (Semi Test Engineering; North Reading, MA)

Teradyne•North Reading, MA

10h

About The Position

We are the global test and automation specialists, powering next-generation technologies through sophisticated solutions. Behind every electronic device you use, Teradyne's test technology ensures your device works right the first time, every time! Our portfolio of automation solutions help manufacturers to develop and deliver products quickly, efficiently and cost-effectively. Together, Teradyne companies deliver manufacturing automation across industries and applications around the world! We attract, develop, and retain a high-performance workforce, comprised of people with diverse backgrounds and a shared drive for excellence. We strive to foster a positive and inclusive work environment that helps employees, and communities, thrive. Our Purpose TERADYNE, where experience meets innovation and driving excellence in every connection. We are fueled by creativity and diversity of thought and in our workforce. Our employees are supported to innovate and learn something new every day. We cultivate a culture of inclusion for all employees that respects their individual strengths, views, and experiences. We believe that our differences enable us to be a better team – one that makes better decisions, drives innovation and delivers better business results. Opportunity Overview Teradyne has an immediate need for a Package Design Engineer with specialty in Signal and Power Integrity for a full-time position with Semiconductor Test Division personnel to develop measurement ASIC products. This hardware engineering position participates as a key person in the hardware design workflow necessary to physically realize complex rf, analog, digital and mixed-signal circuits at both chip, package and board assembly level. The Package Design HW Engineering role serves as a primary interface function between the ASIC Design Team and system hardware engineering and manufacturing teams. This person will play an important role in all phases of hardware development from providing assessments on architectural feasibility, planning for signal and power integrity package signoff validation, performing detailed package and system interconnect optimization and constraint development, working with the PCB design team to insure that performance and manufacturability targets are met, and collaborating with hardware engineering to insure that our simulation models and methodologies can be validated against functional prototypes. The position reports to the Semiconductor Test Engineering ASIC Package Group Manager. All About You We seek individuals who share our passion and determination. Our commitment to customer success drives us to go the extra mile. If you’re ready to join us in this mission, take a closer look at the minimum criteria for the position.

Requirements

A minimum of a MSEE is required, and 7 years of related industry experience
Understanding in the areas of electromagnetic field and transmission line theory, reflection and static timing characterization, PCB and IC Package design for power integrity, high speed digital signaling, analog and RF circuit design.
Experience with the modeling of integrated circuits for signal integrity and timing characterization
Familiarity with IBIS models and the application of the IBIS version 7.0 Standard
Simulation and modelling with Cadence Sigrity, Ansys, Hyperlynx, or ADS.
Knowledge of Cadence Spectre, and SPICE variants (Pspice, Hspice, etc) is a plus.
5 years of experience working on ATE and test strategies for accurate measurement of high-speed signals and power distribution networks.
Understanding of how to go about analyzing passive channels in both time and frequency domain
Experience with concepts of PCB/Package design, design processes, PCB/Package fabrication and materials technology
Familiarity with schematics and constraint driven HW design and development to ensure performance and quality
Knowledge of cutting-edge EDA tools. (Cadence Allegro board design and Concept schematic entry preferred. Allegro Aurora Board Level Signal and Power Integrity Simulation and physical design environment. Virtuoso, Spectre, Hspice, Pspice are a plus)
Experience with the use of time and frequency domain simulation tools and models for full Board level Signal and Power Integrity characterization. Use of 2D and 3D quasi-static, electro-static and full-wave electromagnetic field solvers such as Cadence/Sigrity or Clarity, and board level simulation with Allegro Sigrity SI and PI or Aurora are a plus
Experience with the use of test equipment including Vector Network Analyzer, TDR and high-speed oscilloscopes to validate simulation results and models developed from simulation.
Familiar with S/ABCD/Z/Y- parameter network characterization and ability to apply it to design for highspeed signal and power integrity
Simulation and characterization of Power Distribution Networks, Target Impedance, and DC IRDrop, Joule Heating
Acute attention to detail with excellent organization skills.
Ability to assist with the capture, tracking, and closure of action items resulting from design review meetings.
A solid understanding of the fundamentals of EM and transmission line theory and its application to PCB design, particularly for signal integrity concerns, impedance control / matching, and EMI/EMC mitigation.
A high degree of efficiency using PCB CAD tools with Cadence experience preferred.
Strong analytical, diagnostic and problem-solving skills
Good written communication skills.
Experience delivering presentations in support of design reviews.
Possess the ability to interface with various stakeholders including Package Aggregators, Package Substrate and PCB assembly and fabrication, manufacturing engineers, design engineers, and supply line personnel.

Nice To Haves

Knowledge of Cadence Spectre, and SPICE variants (Pspice, Hspice, etc) is a plus.
Knowledge of cutting-edge EDA tools. (Cadence Allegro board design and Concept schematic entry preferred. Allegro Aurora Board Level Signal and Power Integrity Simulation and physical design environment. Virtuoso, Spectre, Hspice, Pspice are a plus)
Experience with the use of time and frequency domain simulation tools and models for full Board level Signal and Power Integrity characterization. Use of 2D and 3D quasi-static, electro-static and full-wave electromagnetic field solvers such as Cadence/Sigrity or Clarity, and board level simulation with Allegro Sigrity SI and PI or Aurora are a plus
A solid understanding of High Voltage engineering and layout expertise of 1kV or higher a plus.
Programming skills (Tcl, Python, Perl, MATLAB, C/C++, C#, Visual Basic, etc) for data analysis and test/simulation automation a plus

Responsibilities

providing assessments on architectural feasibility
planning for signal and power integrity package signoff validation
performing detailed package and system interconnect optimization and constraint development
working with the PCB design team to insure that performance and manufacturability targets are met
collaborating with hardware engineering to insure that our simulation models and methodologies can be validated against functional prototypes

Benefits

Teradyne offers a variety of robust health and well-being benefit programs, including medical, dental, vision, Flexible Spending Accounts, retirement savings plans, life and disability insurance, paid vacation & holidays, tuition assistance programs, and more.

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