Package Design Engineer

Marvell Technology • Santa Clara, CA

2d

About The Position

About Marvell Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities. At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. Your Team, Your Impact We are seeking an experienced Package Designer with expertise in heterogeneous integration. The ideal candidate will have a strong background in semiconductor packaging design to drive Marvell’s Photonic Fabric Package solutions. This role requires cross-functional design collaboration with multiple engineering groups, such as Packaging, ASIC, AMS, Photonics, and external partners to ensure design for manufacturing, assembly, reliability, and cost. What You Can Expect Lead Si/package/PCB/system co-design work collaborating with downstream system design teams and upstream ASIC/PIC designers to develop a portfolio of packages that meets a huge range of performance design points, while optimizing re-use in other Marvell products. Scope all aspects of package substrate design feasibility for multi-chip SiP packaging. Lead all aspects of package layout based on I/O, SI-PI and form factor requirements, including routing, design for reliability, thermal, mechanical, manufacturability, bumping, substrate, material selection, assembly, and support for testing. Meet specifications for high-speed interfaces such as HBM, DDR, PCIe and 56G/112G SerDes. Netlist management for heterogeneous chiplet assemblies using latest EDA solutions. Supporting activities related to production and assembly of IC packages with substrate suppliers and OSATs. Actively participate in qualification of package and board level assembly with sensitivity to physics of failures for high thermo-mechanical reliability, driving appropriate test vehicle definition and design. Drive ideation and innovation of advanced package solutions and specifications with vendors to advance productization efforts by Marvell

Requirements

• BS/MS/PhD in EE/ECE/MSE/ME/ChemE or related disciplines.
• 5-10 years of experience in Semiconductor Packaging Design.
• Extensive experience working with advanced packaging design tools such as Cadence APD.
• Familiarity with MCAD tools such as AutoCAD.
• Familiarity with high density/high performance interconnects in various 2.5D/3D packaging technologies including InFO, CoWoS, FoCoS and EMIB.
• Good understanding of cross-functional packaging areas: Si floor plan, package, board layout and architecture, design rules, BOM, enabling material/process technologies, thermal, mechanical, Signal/Power Integrity, design for manufacturing, assembly, reliability, and cost.
• Proven track record of working with substrate vendors to meet design for manufacturing, yield, and reliability.
• Proven track record of engagement with OSATs to meet assembly requirements and drive new developments to meet new product requirements.
• Familiarity with High Speed Signaling best practices, Signal and Power integrity requirements.
• Strong analytical, problem-solving, cross-functional collaboration, project management, and technical presentation skills.

Nice To Haves

• Expertise in heterogeneous integration, fan-out packaging, chiplet architectures – co-design, layout, and netlist management.
• Knowledge of Signal and Power Integrity.
• Experience in substrate vendor and OSAT assembly engagement to meet manufacturing and assembly requirements.

Responsibilities

• Lead Si/package/PCB/system co-design work collaborating with downstream system design teams and upstream ASIC/PIC designers to develop a portfolio of packages that meets a huge range of performance design points, while optimizing re-use in other Marvell products.
• Scope all aspects of package substrate design feasibility for multi-chip SiP packaging.
• Lead all aspects of package layout based on I/O, SI-PI and form factor requirements, including routing, design for reliability, thermal, mechanical, manufacturability, bumping, substrate, material selection, assembly, and support for testing.
• Meet specifications for high-speed interfaces such as HBM, DDR, PCIe and 56G/112G SerDes.
• Netlist management for heterogeneous chiplet assemblies using latest EDA solutions.
• Supporting activities related to production and assembly of IC packages with substrate suppliers and OSATs.
• Actively participate in qualification of package and board level assembly with sensitivity to physics of failures for high thermo-mechanical reliability, driving appropriate test vehicle definition and design.
• Drive ideation and innovation of advanced package solutions and specifications with vendors to advance productization efforts by Marvell

Benefits

• Marvell is committed to providing exceptional, comprehensive benefits that support our employees at every stage - from internship to retirement and through life’s most important moments.
• Our offerings are built around four key pillars: financial well-being, family support, mental and physical health, and recognition.
• Highlights include an employee stock purchase plan with a 2-year look back, family support programs to help balance work and home life, robust mental health resources to prioritize emotional well-being, and a recognition and service awards to celebrate contributions and milestones.
• We look forward to sharing more with you during the interview process.

What This Job Offers

• Job Type: Full-time
• Career Level: Mid Level
• Number of Employees: 1,001-5,000 employees