Next-Gen, High-Speed Memory Subsystem ASIC Digital Design Engineer

Qualcomm•San Diego, CA

3d•$140,000 - $210,000

About The Position

Next Generation, High-Speed, Memory and Cache Controller and Advanced Memory NoCs based Subsystem Design Team is looking for ASIC Design Engineers for the next generation high speed LPDDR/DDR memory subsystems.. The front end of the DDR controller interfaces to the rest of the system such as CPU, GPU, DSP, Multimedia Processors and the engineer is expected to be responsible for enabling high speed (1Ghz+) designs in QCT products. The candidate will work on architecture, design (RTL coding), and deployment of the next generation, high-speed memory subsystems into QCT products. You will develop or contribute to the development of design specifications and drive the micro-architecture of portions of the logic design. You will implement and deliver RTL and work with verification engineers to deliver high quality designs. You will be responsible for debugging your designs and also provide debug support when integrated into the rest of the chip. Synthesis, Timing Closure, Physical Design Support, Gate Level Simulations, Power Analysis are expected to be key tasks. You will make regular contributions to the overall improvement in design methodology to drive productivity and quality of results.

Requirements

Bachelor's or Masters degree in Science, Engineering, or related field.
5+ years ASIC design, RTL coding, front-end digital design experience
Bachelor's degree in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience.
Master's degree in Science, Engineering, or related field and 3+ years of ASIC design, verification, validation, integration, or related work experience.
PhD in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.

Nice To Haves

3-10 years of ASIC design (RTL coding) Preferred
Exposure to RTL Design Verification flows is a plus
Bachelors degree in Electrical or Computer Engineering and at least 5+ years of experience in high speed digital design Master's degree preferred
Experience with the following:
LPDDR memory and cache controller, NoC based architectures especially the front end interfacing to the CPU, DSP, and multimedia processors
On-chip tightly coupled SRAM & L3 cache controller architecture/design
Experience with x86 or ARM CPU/bus architectures
Ordering of memory transactions and methods to enforce proper ordering in order to conform to ISA architecture specification

Responsibilities

architecture
design (RTL coding)
deployment of the next generation, high-speed memory subsystems into QCT products
develop or contribute to the development of design specifications
drive the micro-architecture of portions of the logic design
implement and deliver RTL
work with verification engineers to deliver high quality designs
debugging your designs
provide debug support when integrated into the rest of the chip
Synthesis
Timing Closure
Physical Design Support
Gate Level Simulations
Power Analysis
make regular contributions to the overall improvement in design methodology to drive productivity and quality of results