Staff Engineer, Digital ASIC Design

Butterfly Network

7d•$175,000 - $200,000•Hybrid

About The Position

The role of the Principal Digital ASIC Designer offers the opportunity to work within the heart of the product development team and founders and to own the core of what will set Butterfly Network apart. This individual will design, implement, and verify digital signal processing, high speed interface, and system-on-a-chip logic for a suite of next-generation products.

Requirements

BS/MS/PhD in EE/CE (or equivalent practical silicon design experience).
8+ years (typical Staff level) in digital IC / ASIC / SoC design with substantial hands-on RTL ownership and at least one major-IP or full-chip tapeout cycle.
Proven ownership of a defined digital IP/subsystem from micro-architecture and RTL implementation through verification closure and tapeout support.
Strong RTL skills in SystemVerilog/Verilog, including pipelined datapaths, control logic/state machines, and high-throughput streaming interfaces.
Experience designing sustained high-throughput datapaths, including buffering/FIFOs, arbitration/backpressure, bandwidth budgeting, and SRAM/memory interface considerations.
Strong understanding of silicon-level design constraints, including clock/reset architecture, CDC/RDC risk mitigation, power-aware design, and PPA tradeoffs.
Effective collaboration with verification to drive functional closure through signoff (SV/UVM and/or Python-based frameworks such as cocotb).
Experience building and using bit-accurate reference models (e.g., Python) to validate fixed-point behavior and enable end-to-end checking.
Experience supporting post-silicon bring-up/debug and silicon correlation, partnering with firmware/validation to root-cause issues and deliver fixes.
Strong cross-functional communication to close hardware–firmware interfaces (register maps, control/status paths, data-plane contracts) with systems/firmware stakeholders.

Nice To Haves

Experience implementing compute-intensive DSP pipelines (e.g., beamforming, filtering, noise reduction, MAC-heavy datapaths) with fixed-point design discipline.
Exposure to ultrasound / medical imaging systems or sensor data acquisition pipelines and image-quality KPIs.
Advanced-node experience (28nm or smaller), including timing sensitivity and third-party IP integration.
(Optional, only if this matches the role) Experience integrating programmable compute subsystems (MPU/accelerator), including control interfaces and memory/bandwidth tradeoffs.

Responsibilities

Develop low-power RTL for large SoCs in an advanced node.
Implement and optimize signal processing algorithms in RTL.
Integrate multiple embedded processor cores into a large design.
Develop efficient high bandwidth on chip data paths.
Other Technology, Architecture, & Productivity duties as assigned

Benefits

Comprehensive health insurance, encompassing dental and vision coverage, is provided to all our employees. As a health-tech company, we prioritize the well-being of our teams. We also contribute to Health Savings Account (HSA) accounts for all enrolled employees on an annual basis.
Comprehensive Employee Assistance Program - we provide access to tools and resources to support your emotional health and day-to-day needs.
401k plan and match - we facilitate your retirement goals.
Eligible employees will have the opportunity to participate in Employee Stock Purchase Plan (ESPP)
Unlimited Paid Time Off + 10 Holiday Days a Year - recharge and come back ready to make an impact
Parental Leave - we aim to provide our employees with time to bond with their growing family, along with additional support for primary caregivers to help transition back to work
Competitive salaried compensation - we value our employees and show it
Equity - we want every employee to be a stakeholder
The opportunity to build a revolutionary healthcare product and save millions of lives!

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