Architect and optimize digital multiphase voltage regulators . Perform gain/phase margin and stability analysis ; architect and design robust loop compensation. Model and simulate regulator behavior (steady‑state & transients) in Simplis/MATLAB/Simulink/SystemVerilog . Define PWM modulation , phase‑management, current sensing, and ripple minimization strategies. Model/Implement/verify control logic with SystemVerilog/Verilog ; collaborate across analog, digital, and mixed‑signal teams. Validate designs via small‑signal and time-domain analysis; drive improvements to feedback systems.
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Job Type
Full-time
Career Level
Entry Level
Number of Employees
5,001-10,000 employees