Lead FPGA Design Engineer

Neurophos • Austin, TX

7h • Onsite

About The Position

We are developing an ultra-high-performance, energy-efficient photonic AI inference system. We’re transforming AI computation with the first-ever metamaterial-based optical processing unit (OPU).
As AI adoption accelerates, data centers face significant power and scalability challenges. Traditional solutions are struggling to keep up, leading to rapidly rising energy consumption and costs. We’re solving both problems with an OPU that integrates over one million micron-scale optical processing components on a single chip. This architecture will deliver up to 100 times the energy efficiency of existing solutions while significantly improving large-scale AI inference performance.
We’ve assembled a world-class team of industry veterans and recently raised a $110M Series A led by Gates Frontier. Participants include M12 (Microsoft’s Venture Fund), Carbon Direct Capital, Aramco Ventures, Bosch Ventures, Tectonic Ventures, Space Capital, and others. We have also been recognized on the EE Times Silicon 100 list for several consecutive years.
Join us and shape the future of optical computing!
Location: Austin, TX. Full-time onsite position.
Position Overview:
We are seeking an experienced and adaptable FPGA Development Lead to join our foundational silicon team. In this capacity, you will serve as the architect of our hardware emulation and validation strategy, bridging RTL design and physical silicon. As an early team member at a rapidly evolving ASIC startup, your responsibilities will extend beyond coding to encompass the entire FPGA lifecycle, including selecting appropriate hardware platforms and executing complex system-level bring-up and post-silicon characterization.

Requirements

• 10+ years of industry experience
• 5+ years of experience in FPGA design and implementation, preferably within an ASIC or high-growth hardware environment.
• Expert-level proficiency in SystemVerilog for synthesis and verification.
• Deep experience with Xilinx Vivado (Synthesis, Place & Route, Timing Closure, and IP Catalog).
• Proven experience implementing and debugging PCIe interfaces, as well as SPI, UART, JTAG, and other common interfaces.
• Startup mindset: the ability to pivot quickly, work independently, and tackle ambiguous technical challenges.
• Strong hands-on experience with board-level bringup and lab debugging.

Nice To Haves

• Experience with scripting languages (Python or Tcl) for automation of FPGA builds and testing.
• Knowledge of SoC architectures and AMBA bus protocols (AXI, AHB).
• Familiarity with high-speed SERDES tuning and signal integrity concepts.

Responsibilities

• Lead the selection and procurement of FPGA prototyping platforms (e.g., HAPS, VCU118, or custom boards) tailored for pre-silicon RTL verification and software development.
• Adapt and implement complex ASIC RTL onto FPGA targets using SystemVerilog.
• Integrate a mix of in-house designs and third-party IP. You will be the expert on Xilinx-specific IP (Vivado IP Integrator, Transceivers, Memory Controllers).
• Design and debug high-speed interfaces, with a specific focus on PCIe Gen 3/4/5 integration and validation.
• Develop FPGA-based "tester" designs to facilitate post-silicon validation, device characterization, and automated testing environments.
• Utilize ChipScope/Vivado Analyzer and external lab equipment (oscilloscopes, logic analyzers) to solve complex timing and functional issues in a real-time environment.

Benefits

• A pivotal role in an innovative startup redefining the future of AI hardware.
• A collaborative and intellectually stimulating work environment.
• Competitive compensation package including equity participation.
• Comprehensive benefits, including health, dental, and vision insurance.
• Opportunities for career growth and future team leadership.
• Access to cutting-edge technology and state-of-the-art facilities.
• Opportunity to publish research and contribute to the field of efficient AI inference.

What This Job Offers

• Job Type: Full-time
• Career Level: Mid Level
• Education Level: No Education Listed