Lead Firmware Engineer

NeurophosAustin, TX
8hOnsite

About The Position

We are developing an ultra-high-performance, energy-efficient photonic AI inference system. We’re transforming AI computation with the first-ever metamaterial-based optical processing unit (OPU). As AI adoption accelerates, data centers face significant power and scalability challenges. Traditional solutions are struggling to keep up, leading to rapidly rising energy consumption and costs. We’re solving both problems with an OPU that integrates over one million micron-scale optical processing components on a single chip. This architecture will deliver up to 100 times the energy efficiency of existing solutions while significantly improving large-scale AI inference performance. We’ve assembled a world-class team of industry veterans and recently raised a $110M Series A led by Gates Frontier. Participants include M12 (Microsoft’s Venture Fund), Carbon Direct Capital, Aramco Ventures, Bosch Ventures, Tectonic Ventures, Space Capital, and others. We have also been recognized on the EE Times Silicon 100 list for several consecutive years. Join us and shape the future of optical computing! Location Austin, TX. Full-time onsite position. Position Overview We are seeking a talented Firmware Engineer to join our engineering team and spearhead our embedded software development. This role focuses on low-level firmware development for our novel LLM accelerator architecture. You will develop the firmware layer that directly controls our custom hybrid optical-electronic compute hardware, ensuring reliable operation and optimal performance.

Requirements

  • Bachelor's degree in Computer Science, Computer Engineering, Electrical Engineering, or related field
  • 10+ years of industry experience
  • 5+ years of professional experience leading efforts for firmware engineering, embedded systems, or low-level systems programming
  • Expert-level proficiency in embedded C++ (essential), Python for tooling and automation
  • Strong experience with embedded systems programming and hardware interfaces
  • Deep understanding of computer architecture, memory hierarchies, and parallel computing concepts
  • Experience with hardware communication protocols and register-level programming.

Nice To Haves

  • Master’s degree in CS/EE (or related) with expertise in high-performance, low-latency system design, including power and thermal optimization.
  • Deep knowledge of embedded processor architectures (ARM, RISC-V), high-speed interfaces (AXI, PCIe, AMBA), and the ability to read RTL for HW/SW co-design.
  • Experience building adaptive, multi-node, and multi-processor systems using bare metal, RTOS (Zephyr, FreeRTOS), and shared memory IPC.
  • Familiarity with LLM architectures and hands-on experience programming AI/ML accelerators (GPUs, TPUs, FPGAs).
  • Proficiency in virtual platforms/simulators, cross-compiler toolchains, Docker, and modern agentic AI coding workflows.
  • Proven ability to manage OTA update systems and debug complex parallel/asynchronous programs.

Responsibilities

  • Design and implement toolchains for our custom LLM accelerator architecture
  • Develop optimization strategies that bridge software algorithms to hardware implementations
  • Design and implement custom compiler components, including IR dialects, graph transformations, and lowering passes
  • Optimize computational graphs and memory access patterns for our hardware architecture
  • Integrate with existing ML frameworks (e.g., PyTorch, JAX, Triton).
  • Build and maintain test infrastructure to ensure compiler correctness and performance

Benefits

  • A pivotal role in an innovative startup redefining the future of AI hardware.
  • A collaborative and intellectually stimulating work environment.
  • Competitive compensation package including equity participation.
  • Comprehensive benefits, including health, dental, and vision insurance.
  • Opportunities for career growth and future team leadership.
  • Access to cutting-edge technology and state-of-the-art facilities.
  • Opportunity to publish research and contribute to the field of efficient AI inference.
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