Lead Firmware Engineer

STR•Woburn, MA

About The Position

System Development Division (SDD) is focused on delivering National Defense capabilities by driving mission-focused strategies to develop advanced technology systems enabling enduring products and solutions focused on achieving the customer vision. Our programs deliver sustainable, reliable, and cost-efficient capabilities focused on end-customer needs that function in operationally relevant environments and timeframes. SDD considers the entire lifecycle of the solution, from conceptualization and architecting, through development to deployment, while leveraging novel technologies to deliver first-of-a-kind systems. SDD is seeking a Lead Firmware Engineer with a strong understanding of digital signal processing as applicable to radar to implement complex system algorithms and interfaces in FPGAs for Radar and EW systems. Applicable projects span all levels of maturity from initial concept generation through design, prototype, development, test, and transition to production. In this role, you will implement, test, and verify designs through simulation and lab test. These FPGA designs could include signal processing across very wide bands, high data rate interfaces, serial interfaces, and complex control logic. Additionally, you will support the effort to evaluate current and future system capabilities, identify improved applications and techniques, and ultimately recommend solutions. This position requires skills in working with multidisciplinary teams, supporting development and test activities, as well as technical proficiency in relevant technologies. Strong interpersonal, communication, and technical skills are also required. Applicants are expected to be self-motivated, detail oriented and have a demonstrated ability to effectively communicate with all levels of management and individual contributors on the program team through strong written and verbal communication skills.

Requirements

This position requires the ability to obtain a Top Secret (TS) security clearance, for which U.S. citizenship is needed by U.S. Government
Bachelor’s degree and at least 7 years of applicable experience, a Master’s degree and at least 5 years of applicable experience, or PhD and at least 2 years of applicable experience. Equivalent experience will be considered.
Experience with FPGA and SoC design entry using Verilog or VHDL
Experience implementing digital signal processing techniques, filter design, FFT/DFT, fixed-point optimization
Experience with design flow for Xilinx and/or Intel FPGAs
Experience with simulation tools such as ModelSim/Questa, VCS, or Incisive
Demonstrated desire to successfully pursue new challenges, improve and broaden technical skills, seek greater responsibilities, and increase individual value to the organization
Capable of effectively working in a team environment, often under tight deadlines

Nice To Haves

Active Security Clearance at the Secret or Top Secret level
Proficient with Xilinx or Altera SoC platforms
Proficient with FPGA or ASIC RTL design entry
Strong background and experience with industry best practices and version control
Proficient with complex timing closure
Experience with Matlab, Python, or C/C++
Experience with interfacing to high speed DACs and ADCs
Knowledge of pulse compression, Doppler processing, beamforming, detection algorithms
Previous experience with RFSoC or Analog Devices ADC/DAC
Understanding of RF Systems, specifically radar or EW

Responsibilities

Map system-level radar requirements and algorithms to efficient FPGA architectures
Design and implement radar signal processing algorithms in FPGAs (pulse compression, FFT processing, CFAR detection, beamforming, Doppler processing)
Develop high-throughput, low-latency processing architectures for real-time radar applications
Implement waveform generation, digital down-conversion, and channelization in FPGA fabric
Design and optimize pipelined arithmetic units and custom DSP blocks for radar processing
Interface FPGAs with high-speed ADCs/DACs for radar RF front-end integration
Validating designs with simulation and verification techniques before hardware integration
Participating in FPGA development process improvement
Supporting full life cycle of development and integration of FPGA firmware into hardware systems
Creating and maintaining design documentation and test plans
Delivering technical briefings to a range of internal and external stakeholders
Coordinating with program managers and technical leads to manage task schedules and budgets
Providing mentorship to more junior engineers to accelerate their technical and professional development
Building and maintaining high-performing and empowered technical teams