Layout Engineer (7394)

TSMC • San Jose, CA

2d • Onsite

About The Position

Coordinating the design changes, design fitting issues, and other technical data to ensure customers’ designs can fit TSMC’s production flow and procedures. Specific tasks include but are not limited to acting as liaison between customer and TSMC fab manufacturing staff; providing training and on-site support to TSMC’s U.S. Customers of TSMC specific advanced processing SRAM block layout, utilizing knowledge of TSMC’s design rules; implementing blocks of customer’s chip, covering floor plan, timing and noise closure and power planning. Providing all of IP in DDRIO layout floorplan and layout guideline.

Requirements

• Master’s degree or foreign equivalent in Electrical Engineering, Electrical and Computer Engineering or related field, and two (2) years of experience in a related position.
• knowledge of chip design processes and procedures
• knowledge of innovation for 3D-chip stacking
• experience with chip design
• experience with advance technologies design, especially in A14/2nm/3nm/5nm/7nm tech nodes in analog IP and SRAM Macro, and DDRIO
• experience with IC layout tools, physical design and verification flow

Responsibilities

• acting as liaison between customer and TSMC fab manufacturing staff
• providing training and on-site support to TSMC’s U.S. Customers of TSMC specific advanced processing SRAM block layout, utilizing knowledge of TSMC’s design rules
• implementing blocks of customer’s chip, covering floor plan, timing and noise closure and power planning
• Providing all of IP in DDRIO layout floorplan and layout guideline

What This Job Offers

• Job Type: Full-time
• Career Level: Mid Level