Ayar Labs, the global leader in optical I/O chiplets, is harnessing silicon photonics to revolutionize the scaling of AI compute hardware. Our Link Design and Architecture team is responsible for ensuring the robustness and performance of the optical links that power our technology. We are looking for a motivated graduate intern to bridge the gap between large-scale data analysis and optical link models. In this role, you will analyze measurement data from our assembly process to break down sources of variation, specifically focusing on fiber-to-chip coupling efficiency. You will use these insights to improve our optical link budgets and simulation models. Furthermore, you will have the opportunity to validate your analysis through hands-on experimental work in the lab. The projects are tailored to your experience and interests, and you will be mentored by a senior engineer as you work alongside Ayar Labs engineers to help drive the optical I/O revolution.