Intern - ATE Process Engineer ID1

Micron TechnologyBoise, ID
1dOnsite

About The Position

Finish the required safety training and adhere to safety policies and laws. Ensure proper tool documentation and update reaction mechanisms as needed. Supervise and resolve issues impacting yield, excursions, defects, or output loss. Apply SPC, FDC, and 8D methodologies to optimize processes and improve tool availability. Analyze data using engineering knowledge and visualization tools to make critical process decisions. Perform project work to optimize wafer processing and increase wafer outs. Update or create procedures to align with area and global practices. Current student in a STEM degree program with an expected graduation timeframe of May-June 2027. Ability to work ~20 hours per week on‑site in Boise, ID. Availability to commit to a minimum internship duration of 6-8 months, with a preferred timeline of September 2026 through May/June 2027.

Requirements

  • Current student in a STEM degree program with an expected graduation timeframe of May-June 2027
  • Ability to work ~20 hours per week on‑site in Boise, ID
  • Availability to commit to a minimum internship duration of 6-8 months, with a preferred timeline of September 2026 through May/June 2027
  • Understanding of Statistical Process Control (SPC) and Design of Experiments (DOE)
  • Proficiency in one or more scripting, programming, or visualization tools such as Python, Java, Tableau, Matlab, or Microsoft Suite
  • Excellent verbal and written communication skills
  • Experience with data collection, warehousing systems, and data cleansing
  • Hands-on experience in data analytics and database querying
  • Intermediate understanding of semiconductor Fab processes and equipment
  • Strong time management, organization, and prioritization skills

Responsibilities

  • Finish required safety training and adhere to safety policies and laws
  • Ensure proper tool documentation and update reaction mechanisms as needed
  • Supervise and resolve issues impacting yield, excursions, defects, or output loss
  • Apply SPC, FDC, and 8D methodologies to optimize processes and improve tool availability
  • Analyze data using engineering knowledge and visualization tools to make critical process decisions
  • Perform project work to optimize wafer processing and increase wafer outs
  • Update or create procedures to align with area and global practices
© 2024 Teal Labs, Inc
Privacy PolicyTerms of Service