Interconnect Micro-architect/RTL Design Engineer

Advanced Micro Devices, Inc•Boxborough, MA

38d•Hybrid

About The Position

As a member of the Infinity Fabric Architecture and RTL team, you will help build the next generation coherent interconnect to provide connectivity between CPU, GPU and special purpose accelerators. Every product that AMD sells has its own custom-designed Infinity Data Fabric, so this role gives an engineer the opportunity to work on a broad array of products that address a variety of markets, including traditional servers, high performance computing, client desktop and laptop PCs, machine intelligence, graphics, console gaming, embedded, and customer-specific applications. It is a challenging position that involves working at a fast pace of innovation on the cutting edge of technology. Come join the AMD team! The Person: You are an experienced RTL design engineer with strong communication skills. You have a passion for modern, complex processor architecture, digital design as well as verification/design quality. You are a team player who has excellent communication skills, strong analytical & problem-solving skills and are willing to learn and ready to take on problems. You have a global mindset and ability to work in a multi – site environment are keys to being successful in this role.

Requirements

Proven experience designing logic blocks in CPU, GPU, NOC, or cache designs.
Excellent knowledge of Verilog and System Verilog
Working knowledge of C, C++ and a scripting language like Perl or Python
Strong understanding of digital electronics and high-speed designs(>1GHz).
Good understanding of multi-processor coherency, memory ordering, i/o ordering, interrupts, MMU and caches.
Good debugging and analytical skills
Exposure to Design for Test, understanding of scan concepts and writing DFT friendly RTL
BS, MS, or PhD degree in Electrical or Computer engineering preferred.

Nice To Haves

Working knowledge of x86 or ARM ISA is a plus.

Responsibilities

Early architectural/performance exploration through micro architectural definition and design.
Optimize the design to meet power, performance, area and timing requirements.
Write easily readable and synthesizable Verilog RTL.
Run some unit level testing to deliver quality code to the Design Verification Team.
Create assertions to improve coverage and cover points to analyze coverage of the design.
Create well written block level design documentation.
Participate in post silicon functional and performance debug and tuning.