HW Engineering Intern - PCB Layout Automation & AI Tooling

d-Matrix • Santa Clara, CA

1d • Hybrid

About The Position

At d-Matrix, we are building the future of AI compute. To do that faster, we need to rethink how hardware is designed. We are looking for a forward-thinking Hardware Engineering Intern to join our team and focus on the cutting edge of EDA (Electronic Design Automation) and AI-driven layout.
Your mission will be to evaluate, integrate, and automate PCB layout workflows using emerging AI-agent technologies and generative AI design tools. You will bridge the gap between traditional hardware design and the future of automated, agentic workflows.

Requirements

• Current Student: Pursuing a BS, MS, or PhD in Electrical Engineering, Computer Engineering, or Computer Science.
• PCB Fundamentals: Basic understanding of PCB design flow (Schematic -> Layout -> Fabrication) and familiarity with at least one EDA tool (Allegro, Altium, or KiCad).
• Programming Skills: Strong proficiency in Python. Experience with APIs, data parsing (JSON/XML), or automated tool-chaining is highly preferred.
• First-Principles Thinking: A passion for challenging the status quo of "how things have always been done" in hardware design.

Nice To Haves

• Familiarity with AI/ML concepts, particularly Reinforcement Learning or Generative Models applied to physical design.
• Experience with GitHub and version control for hardware projects.
• Exposure to high-speed design concepts (PCIe, DDR, SerDes).

Responsibilities

• AI Tool Evaluation: Lead the internal evaluation of AI-driven layout platforms.
• Benchmarking their ability to handle high-speed constraints, complex stack-ups, and power delivery requirements against traditional manual routing.
• Workflow Automation: Develop scripts (Python, SKILL, or TCL) to bridge the gap between d-Matrix’s standard EDA tools (Cadence Allegro/OrCAD) and AI layout agents.
• PCB Design Support: Assist Senior Layout Engineers in preparing design data (schematics, netlists, and constraint files) for automated routing engines.
• Constraint Translation: Work on "translating" complex hardware constraints (differential pairs, length matching, and Z_target} for PDN) into formats that AI agents can ingest and execute accurately.
• Performance Analysis: Conduct post-layout analysis on AI-generated designs, comparing Signal Integrity (SI) and Power Integrity (PI) metrics against human-designed baselines.

What This Job Offers

• Career Level: Intern
• Education Level: Ph.D. or professional degree