Head of Silicon Package Reliability

Google • Mountain View, CA

2d • $221,000 - $311,000

About The Position

As a Reliability Engineer, you will play a key role in creating new consumer electronic products that meet a high bar for reliability and performance. You will work closely with the product management and design engineering teams to define standards, specify tests, and then supervise test execution and failure analysis. A broad engineering background and command of statistical methods will help to inform design of new products. Your strong people management and communication skills will be key to ensuring adoption of your technical recommendations. Google engineers develop the next-generation technologies that change how users connect, explore, and interact with information and one another. In this role, you will develop new products that are used by people. The US base salary range for this full-time position is $221,000-$311,000 + bonus + equity + benefits. Our salary ranges are determined by role, level, and location. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your preferred location during the hiring process. Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits. Learn more about benefits at Google .

Requirements

• Bachelor's degree in Hardware Engineering or equivalent practical experience.
• 12 years of experience in Silicon/SOC reliability spanning transistors, Back-end interconnects, silicon, package interconnects reliability, and package board interactions.
• 10 years of experience managing a team across multiple silicon and packaging quality and reliability domains.
• 6 years of experience in an engineering leadership role working with and managing executive stakeholders across areas and disciplines.

Nice To Haves

• Master's degree or PhD in Hardware Engineering.
• Experience in leading reliability program reviews with executives, right sizing and prioritizing technical issues, driving cross-functional teams towards corrective actions and mitigations as well as managing escalations with executive leadership.
• Experience in applying design for reliability techniques (Modeling, DFMEA) and reliability modeling techniques, such as Reliability Block Diagram, Weibull, Reliability Growth Models.
• Experience with failure analysis techniques for electrical, mechanical or optical components.
• Experience shipping multiple silicon and package generations in a reliability lead role.
• Experience in modeling and reliability statistics for silicon, interconnects and packaging failure modes.

Responsibilities

• Provide technical leadership to a silicon/package reliability engineering team, through end-to-end product life-cycle, from early engagement and design for reliability through validation into sustaining phases.
• Collaborate with silicon engineering, operations, platforms and validation teams to execute reliability testing across DFR, validation and testing phases at the silicon, package and board levels.
• Work with cross-functional teams to translate System-on-Chip mission profiles into reliability test plans and models using reliability statistics and Physics of Failure models.
• Lead team on statistical data analysis, High Temperature Operating Life (HTOL) testing, modeling, and risk predictions.
• Develop reliability performance metrics and lead management reviews to review progress against those metrics.
• Lead reliability test planning, methodology and execution for all aspects of the product.
• Set expectations with individuals based on their role, meet regularly to discuss performance, development, and feedback/coaching.

What This Job Offers

• Job Type: Full-time
• Career Level: Executive
• Number of Employees: 5,001-10,000 employees