Hardware Security Engineer (Devices & Services Security)

AG Consulting Partners, Inc.•Seattle, WA

6d•$160,000 - $250,000•Onsite

About The Position

We are actively seeking two senior candidates who are authorized to work in the United States without visa sponsorship or E-Verify requirements. This role is fully onsite, five (5) days per week, and candidates must be located within a commutable distance (approximately 30 miles) of the client campus in downtown Seattle, WA. Role Overview The ideal candidate brings deep domain expertise and is able to articulate decision rationale effectively, contributing to the development of both technical and business solutions. As a recognized subject matter expert, the Hardware Security Engineer is frequently consulted on cross-functional initiatives and operates independently with minimal oversight. This role earns trust and respect from engineering teams and senior stakeholders through consistent leadership, accountability, and strategic insight, while ensuring delivery excellence across the program lifecycle. Please note: This is a 12-month engagement and requires being onsite five (5) days per week in Seattle, WA. Candidates must reside within a 30-mile radius of the client campus and be authorized to work in the U.S. without sponsorship. As a Hardware Security Engineer for AG Consulting Partners, a typical day might include the following:

Requirements

5+ years of experience in hardware security, embedded systems security, or similar
Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related technical field
Strong knowledge of secure boot implementations, cryptography (RSA, AES, HMAC, PQC), and hardware security architectures (e.g. ARM TrustZone or Intel SGX)
Experience with manufacturing security processes, including secret provisioning and secure production flows
Knowledge of debug interface security (JTAG, BDM), anti-rollback mechanisms, and fault injection protection
Familiarity with circuit design, physical attack mitigation techniques, and consumer electronic devices
Experience with hardware security testing tools and methodologies

Nice To Haves

Master's degree in relevant technical field or equivalent advanced experience
Experience with DRM implementations and content protection systems
Knowledge of side-channel attack analysis and associated countermeasures
Experience with penetration testing or hacking consumer electronic devices
Experience writing technical documents, project plans and progress reports to leadership and to stakeholders

Responsibilities

Analyzing System-on-a-Chip (SoC) security architectures to validate secure boot chains, root-of-trust enforcement, anti-rollback protections, and cryptographic controls at the silicon level.
Validating hardware security requirements through hands-on testing of physical devices, evaluation boards, and chip samples across development and production lifecycles.
Executing hardware security testing techniques, including fault injection attempts, debug interface probing (JTAG/BDM), and resistance validation against physical attacks.
Reviewing schematics, board layouts, and hardware designs to ensure correct implementation of secure key storage, tamper mitigations, and debug access restrictions.
Verifying manufacturing security processes by assessing secure provisioning flows, key injection procedures, and production lifecycle state transitions.
Inspecting manufactured hardware samples to detect unauthorized component substitution, malicious modification, or deviations from approved security designs.
Assessing cryptographic implementations (RSA, AES, HMAC, PQC) embedded in hardware and firmware to confirm secure key handling and isolation.
Collaborating with silicon vendors, OEMs, and manufacturing partners to remediate security findings and validate corrective actions at the device and chip level.
Identifying systemic hardware security risks by correlating lab results, manufacturing data, and field observations across large-scale device deployments.
Documenting security assessments, validation outcomes, and risk mitigation plans in technical reports and communicating findings to engineering and leadership stakeholders.