Hardware FPGA Design Engineer - Acacia (Hybrid)

Cisco • Maynard, MA

7d • Hybrid

About The Position

Acacia, now part of Cisco, designs intelligent optical transceivers using sophisticated signal processing and photonic integration for >1T bit speed fiber optic transmission market deployed in data center, metro, long-haul and ultra-long haul telecommunication networks. The team is a versatile and upbeat team of enthusiastic engineers in an environment where team members experience mutual enhancement and improvement. You will have the opportunity to collaborate cross-functionally with our Hardware, Software, Optics, and manufacturing teams.

You are a high-energy FGPA Design engineer who loves to work on complex communications products. You are a team player with a startup mentality who loves to challenge the status quo with creation and innovation. You can figure things out by yourself, but you are comfortable to participate in our friendly and team-oriented collaboration approach to learn from others. You are not shy to point out how we can be more effective as a team, and yet you are open to similar suggestions by your team members to foster mutual growth for all.

Requirements

• 5+ years of FPGA design and verification experience
• Experience in Verilog RTL coding and synthesis for FPGAs
• Experience with Python and Linux
• Experience designing interfaces with Processors, SPI & I2C devices, MDIO, high speed SERDES, etc.
• Experience in Xilinx® design tool chain for design, place, and route (ISE®, Vivado® suite)

Nice To Haves

• C/C++ and experience coding with embedded MCUs
• Experience in designs and timing closure with multiple clock domains
• Experience work in labs and experience with test equipment to help with board level and FPGA bring up
• Experience with analog components (OpAmps, DACs/ADCs, etc.)
• Experience implementing digital control loops and DSP functions
• Experience with Xilinx FPGA families such as Ultrascale+
• Experience with Synopsys VCS simulation and Synplify® synthesis tools for FPGAs
• Expertise in creating FPGA implementations from ASIC RTL code
• Expertise in digital design of standard cell ASICs
• Experience presenting technical information to technical and non-technical audiences.

Responsibilities

• Design/Verify FGPAs For Acacia's Product and Evaluation platform
• Write Python routines for Test Development and Automation
• Contribute to FPGA Emulation of ASIC Blocks
• Contribute to our custom ASIC RTL code

Benefits

• U.S. employees are offered benefits, subject to Cisco’s plan eligibility rules, which include medical, dental and vision insurance, a 401(k) plan with a Cisco matching contribution, paid parental leave, short and long-term disability coverage, and basic life insurance.
• Employees may be eligible to receive grants of Cisco restricted stock units, which vest following continued employment with Cisco for defined periods of time.
• U.S. employees are eligible for paid time away as described below, subject to Cisco’s policies: 10 paid holidays per full calendar year, plus 1 floating holiday for non-exempt employees 1 paid day off for employee’s birthday, paid year-end holiday shutdown, and 4 paid days off for personal wellness determined by Cisco
• Non-exempt employees receive 16 days of paid vacation time per full calendar year, accrued at rate of 4.92 hours per pay period for full-time employees
• Exempt employees participate in Cisco’s flexible vacation time off program, which has no defined limit on how much vacation time eligible employees may use (subject to availability and some business limitations)
• 80 hours of sick time off provided on hire date and each January 1st thereafter, and up to 80 hours of unused sick time carried forward from one calendar year to the next
• Additional paid time away may be requested to deal with critical or emergency issues for family members
• Optional 10 paid days per full calendar year to volunteer
• For non-sales roles, employees are also eligible to earn annual bonuses subject to Cisco’s policies.

What This Job Offers

• Job Type: Full-time
• Career Level: Mid Level