SageCor Solutions-posted 28 days ago
Full-time • Entry Level
Onsite • Fort Meade, MD

Serving Maryland and the Greater Washington D.C. area, SageCor Solutions (SageCor) is a growing company bringing complete engineering services and true full lifecycle System Engineering services to areas requiring (or desiring) nationally-recognized expertise in high performance computing, large data analytics and cutting edge information technologies. Active TS/SCI w/ Polygraph required.

  • May provide FPGA support for vulnerability assessments, circuit analysis and/or reverse engineering efforts
  • Must possess an active TS/SCI Clearance with Full-Scope Polygraph
  • Experience using VHDL, Verilog or SystemVerilog RTL Coding (for design and/or analysis of digital circuits)
  • Experience with FPGA Design, synthesis, P&R tools (ex Vivado, Quartus)
  • Experience utilizing Verilog/System and Verilog test bench development
  • Experience working with Linux/Windows OS
  • Knowledge of design simulation tools (Mentor, Cadence, Synopsys - 1 or more)
  • Strong oral/written communication
  • Location is onsite at Fort Meade, MD
  • May have up to 20 hours of remote work per week once established and approved by the Customer
  • Multiple openings for Junior, Senior, Principal and Sr. Principal Engineers: Minimum three (3) years’ experience as a Design Engineer in integrated circuit or microelectronic component design or reverse engineering of the same is required.
  • Bachelor’s degree in electrical engineering or computer engineering from an accredited college or university is required.
  • Five (5) years of additional hardware design engineering experience may be substituted for a bachelor’s degree.
  • Experience with C/C++, Bash, Tcl/TK, GitLab
  • Experience with FPGA design using Xilinx's Vivado Tool Suite
  • Experience using soft/hard IP cores in FPGAs/ASICs (ex Zynq or Microblaze or RISC processors, memories, flash/NVM)
  • Exposure to embedded software development
  • Exposure to PCB design and development
  • Python scripting
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