GPU Validation and Emulation Engineer, Senior

Qualcomm•Santa Clara, CA

15d

About The Position

As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm GPU Engineer, you may architect, design, implement, verify, and/or optimize the performance and power of GPU cores. Qualcomm Engineers collaborate with cross-functional teams to meet and exceed customer needs. Synthesize the Verilog RTL and create models and compile them to emulators like Veloce/Palladium/Zebu and/or FPGA platforms Develop all aspects of hardware emulator implementation, with emphasis on design partitioning, synthesis, place and route, timing analysis & run time performance. Drive debug failures on emulator using latest technologies. Work with designers and SW driver team for testplan and debug. Work with tool vendors and push the methodology to improve the area/performance of the synthesized FPGA RTL. Work on third-party IP integration and system-level debugging. System level RTL simulation & design verification. Support chip bring up and post silicon debug. Debug functional and timing models.

Requirements

Bachelor's degree in Computer Engineering, Computer Science, Electrical Engineering, or related field and 2+ years of Software Engineering, Hardware Engineering, Systems Engineering, or related work experience.
OR Master's degree in Computer Engineering, Computer Science, Electrical Engineering, or related field and 1+ year of Software Engineering, Hardware Engineering, Systems Engineering, or related work experience.
OR PhD in Computer Engineering, Computer Science, Electrical Engineering, or related field.

Nice To Haves

Bachelors degree in Science, Engineering, or closely related field
1+ years of hands on experience in emulation/simulation acceleration/FPGA.
1+ years in Design validation/Post-Silicon debug.
1+ years of hands on experience in creating high performance & area efficient emulation environments from RTL.
1+ years of hands on emulator platforms, platform bringup, digital design, verification, debugging, and waveform viewers
1+ Hardware emulators, such as Palladium, ZeBu, Veloce, or FPGA systems based on Xilinx or Altera FPGAs
1+ Emulation methodologies, including in-circuit emulation, hybrid systems, or simulation acceleration
MS degree in Electrical Engineering or equivalent; 1 year of practical experience
Design Verification knowledge – UVM/System Verilog preferred
Knowledge of GPU/CPU/DDR/Bus preferred
Verilog and System Verilog experience.
Debugging system-level software, Debug RTL
Programming skills in C and C++
Scripting in Python, Tcl, or Perl
Knowledge of Vendor Emulation tools/Xilinx tools/Synthesis tools

Responsibilities

Synthesize the Verilog RTL and create models and compile them to emulators like Veloce/Palladium/Zebu and/or FPGA platforms
Develop all aspects of hardware emulator implementation, with emphasis on design partitioning, synthesis, place and route, timing analysis & run time performance.
Drive debug failures on emulator using latest technologies. Work with designers and SW driver team for testplan and debug.
Work with tool vendors and push the methodology to improve the area/performance of the synthesized FPGA RTL.
Work on third-party IP integration and system-level debugging.
System level RTL simulation & design verification.
Support chip bring up and post silicon debug.
Debug functional and timing models.