About The Position

The Design Implementation Engineer will work in Qualcomm's Adreno GPU team and will be responsible for managing all aspect of frontend implementation design challenges and methodology. The successful applicant will integrate, implement and deliver state of the art GPU cores and will be working closely with the microarchitecture and physical design teams to meet very aggressive Power, Performance, and Area (PPA) targets. The successful candidate will possess in-depth understanding of ASIC design flow and the challenges posed by advanced nanometer technologies. The candidate is expected to be able to demonstrate the following: Experience with digital design and RTL synthesis Experience with EDA tools such as: Design Compiler, Fusion Compiler, Genus, Innovus, Conformal LEC, Formality, and PrimeTime Experience with power vector generation and power analysis Ability to collaborate with RTL designers to improve power and performance Solid scripting skills using Tcl or Python Excellent analytical and communication skills, self-motivated

Requirements

  • Experience with digital design and RTL synthesis
  • Experience with EDA tools such as: Design Compiler, Fusion Compiler, Genus, Innovus, Conformal LEC, Formality, and PrimeTime
  • Experience with power vector generation and power analysis
  • Ability to collaborate with RTL designers to improve power and performance
  • Solid scripting skills using Tcl or Python
  • Excellent analytical and communication skills, self-motivated
  • Bachelor’s degree in Electrical/Computer Engineering or related field with 7+ years of direct frontend implementation and physical design work experience OR Master’s degree in Electrical/Computer Engineering or related field with 6+ years of direct frontend implementation and physical design work experience OR PhD in Electrical/Computer Engineering or related field with 5+ years of direct frontend implementation and physical design work experience
  • Strong background and experience working with industry standard synthesis and place-and-route tools
  • Experience with process technology nodes below 10 nm
  • Bachelor's degree in Computer Engineering, Computer Science, Electrical Engineering, or related field and 4+ years of Software Engineering, Hardware Engineering, Systems Engineering, or related work experience.
  • Master's degree in Computer Engineering, Computer Science, Electrical Engineering, or related field and 3+ years of Software Engineering, Hardware Engineering, Systems Engineering, or related work experience.
  • PhD in Computer Engineering, Computer Science, Electrical Engineering, or related field and 2+ years of Software Engineering, Hardware Engineering, Systems Engineering, or related work experience.

Nice To Haves

  • Knowledge of UPF
  • Knowledge of advanced process nodes, e.g. 3 nm and below
  • Understanding of GPU microarchitecture
  • Experience with leading a high performance team to push aggressive PPA targets is advantageous

Responsibilities

  • managing all aspect of frontend implementation design challenges and methodology
  • integrate, implement and deliver state of the art GPU cores
  • working closely with the microarchitecture and physical design teams to meet very aggressive Power, Performance, and Area (PPA) targets

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What This Job Offers

Job Type

Full-time

Career Level

Mid Level

Number of Employees

5,001-10,000 employees

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