GenAI Physical Synthesis Engineer
About The Position
Do you love building intelligent solutions that revolutionize chip design? Do you see the transformative potential of GenAI in physical synthesis workflows? As part of our Silicon Technologies group, you'll pioneer the next generation of AI-powered design automation tools that will accelerate our processor and SoC development. You'll harness cutting-edge GenAI and agentic technologies to solve complex physical synthesis challenges, enabling Apple to deliver even more powerful and efficient silicon. Joining this team means you'll be at the forefront of merging artificial intelligence with chip design, creating intelligent agents that will reshape how we build the technology that powers Apple's beloved devices! You will apply your expertise in GenAI, agentic frameworks, and physical synthesis to develop intelligent automation solutions that transform our RTL-to-GDS implementation flows. You will be directly responsible for creating AI-powered agents using technologies like Model Context Protocol (MCP) that can autonomously optimize physical synthesis processes, predict design challenges, and recommend solutions.
Requirements
- Experience with GenAI frameworks, large language models, and AI agent development
- Experience with industry standard Synthesis tools such as Fusion Compiler or Genus
- Scripting skills in TCL, Python, or Perl for EDA tool automation
- Minimum requirement of BS + 3 years of relevant industry experience
Nice To Haves
- Understanding of physical synthesis concepts and CAD flows
- Experience in Python AI/ML libraries (PyTorch, TensorFlow, Transformers) and MCP or similar agentic frameworks
- Experience developing AI agents or autonomous systems for technical domains
- Knowledge of prompt engineering, RAG (Retrieval-Augmented Generation), and fine-tuning techniques
- Experience with agentic AI frameworks beyond MCP (AutoGen, CrewAI, LangChain agents, etc.)
- Background in CAD flow or frontend methodology development combined with AI/ML expertise
- Experience with Low Power implementation flows (UPF) and AI-driven power optimization
- Familiarity with logical equivalence tools (Conformal LEC, Formality) and opportunities for AI enhancement
- Knowledge of static timing analysis, place and route tools, and potential AI applications in these domains
- Experience with cloud platforms and distributed AI model deployment
- Publications or demonstrated expertise in AI applications for EDA or chip design
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What This Job Offers
Job Type
Full-time
Career Level
Mid Level
Number of Employees
5,001-10,000 employees
