FPGA Verification Engineer - Avionics

E-Space•Saratoga, CA

5d•Onsite

About The Position

Ready to make connectivity from space universally accessible, secure and actionable? Then you’ve come to the right place! E-Space is bridging Earth and space to enable hyper-scaled deployments of Internet of Things (IoT) solutions and services. We are building a highly-advanced low Earth orbit (LEO) space system that will fundamentally change the design, economics, manufacturing and service delivery associated with traditional satellite and terrestrial IoT systems. We’re intentional, we’re unapologetically curious and we’re 100% committed to innovate space-based communications and deliver actionable intelligence that will expand global economies, protect space and our planet and enhance our overall quality of life. We are hiring FPGA Verification Engineers to build and maintain the verification infrastructure for satellite avionics FPGA designs. You will develop UVM-based testbenches, create coverage-driven verification plans, and ensure RTL correctness for flight-critical FPGA firmware across multiple subsystems. This role is instrumental in establishing a rigorous verification methodology for the program.

Requirements

Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field.
4+ years of experience in FPGA or ASIC verification.
Strong expertise in SystemVerilog and UVM-based verification methodology.
Experience building UVM agents, environments, and generating constrained-random stimulus.
Proficiency with at least one industry-standard RTL simulator.
Understanding of functional coverage techniques and coverage-driven verification.
Ability to read and understand PCB schematics and hardware interfaces for test development.

Nice To Haves

Experience verifying designs for space, aerospace, or high-reliability applications.
Familiarity with formal verification tools.
Background in embedded software interaction with FPGA firmware.
Experience with continuous integration workflows for verification regressions.
Proficiency in Python, TCL, or shell scripting for test automation and infrastructure.
Exposure to DFMEA and high-reliability digital design review processes.

Responsibilities

Develop UVM-based verification environments including agents, scoreboards, and bit-accurate reference models.
Create and maintain a reusable, extendable UVM framework supporting multiple FPGA targets and device configurations.
Write verification plans derived from requirements specifications and architectural documents.
Develop functional coverage models and drive coverage closure for all FPGA designs.
Perform RTL simulation using industry-standard tools.
Implement clock-domain crossing verification and timing/stability analysis.
Apply lint and static-analysis tools to identify design issues early in the development cycle.
Support hardware bring-up by creating tests that model and recreate hardware interactions in simulation.
Document verification results, coverage metrics, and test plans with clear technical writing.
Collaborate with FPGA designers and system engineers to refine requirements and close verification gaps.