FPGA Design Scientist

ASML • San Diego, CA

9d • Onsite

About The Position

Introduction to the job As an FPGA design scientist, you will participate in a cross-functional and collaborative team to specify and create custom digital circuit designs, simulate, implement and support hardware testing for future ASML’s EUV Source with a strong focus on real‑time control, diagnostics, and system‑level FPGA solutions envisioned in production EUV source platforms. You will be contributing in a research environment that strongly emphasizes on novel, innovative ideas to the N+3 generation of EUV source product, while delivering robust, testable FPGA implementations that also bridge advanced concepts into deployable EUV source firmware for current and next‑generation systems (N+1 / N+2). Role and responsibilities Responsible for contributing to, and translating requirements, into qualified firmware design solutions, with a focus on innovation and out-of-the-box thinking. Define and execute RTL design and implementation, verification, block-level simulations, hardware integration / test throughout the FPGA development process from ideation through volume release. Collaborate with a team of FPGA engineers to realize the solution, including deliverables tracking and peer-reviewing HDL output, from early architecture trade-offs through lab test setups, system integration, and volume-release readiness. Documentation of design solution using standardized templates and guidelines. Collaborate in a complex and fast-paced environment with FPGA design, verification and test engineers as well as adjacent engineering competencies such as software and control engineering. Continually sharpen technical and professional skill-sets through available development programs. Other duties as assigned with subject to change as required at any time.

Requirements

• MS or higher in EE, CS or related engineering fields.
• Minimum of eight (8) years of experience in FPGA design with demonstrated success in full FPGA development cycles; requirement decomposition through realization.
• Demonstrated expertise and experience in FPGA design (VHDL) and Module / Multi-Module verification (System Verilog).
• Ability to complete timing simulation/post route simulation and static timing analysis.
• Strong experience in hardware development tools and IDE for Xilinx devices; additional experience in Altera development tools a plus.
• Ability to utilize lab hardware and IDE cores to debug (ILAs, VIO, SignalTaps, etc.)
• Familiar with SoC, bus topology, AXI, PCIe, PTP, TSN, SRIO and associated IP.
• Familiar with configuration management/version control/build automation.
• Able to abstract requirements into concept and solution space
• Ability to learn and apply new information and/or skills.
• Demonstrated creative problem solving for complex issues.
• Can read and interpret data, information, and documents.
• Track record of completing assignments with attention to detail and high degree of accuracy.
• Proven ability to perform effectively in a demanding environment, within provided timelines, and with changing workloads.
• Results driven; exhibits ownership and accountability.
• Work independently or as part of a team and follow through on assignments with minimal supervision.
• Strong professional communication which is clear and concise.
• Ability to establish and maintain cooperative working relationships with co-workers.

Nice To Haves

• Experience with automated self-checking test bench verification and using UVM framework a plus, with emphasis on deterministic, safety‑critical, and high‑reliability designs used in real‑time EUV source operation.

Responsibilities

• Responsible for contributing to, and translating requirements, into qualified firmware design solutions, with a focus on innovation and out-of-the-box thinking.
• Define and execute RTL design and implementation, verification, block-level simulations, hardware integration / test throughout the FPGA development process from ideation through volume release.
• Collaborate with a team of FPGA engineers to realize the solution, including deliverables tracking and peer-reviewing HDL output, from early architecture trade-offs through lab test setups, system integration, and volume-release readiness.
• Documentation of design solution using standardized templates and guidelines.
• Collaborate in a complex and fast-paced environment with FPGA design, verification and test engineers as well as adjacent engineering competencies such as software and control engineering.
• Continually sharpen technical and professional skill-sets through available development programs.
• Other duties as assigned with subject to change as required at any time.

Benefits

• The Company offers employees and their families, medical, dental, vision, and basic life insurance.
• Employees are able to participate in the Company’s 401k plan.
• Employees will also receive eight (8) hours of vacation leave every month and (13) paid holidays throughout the calendar year.

What This Job Offers

• Job Type: Full-time
• Career Level: Mid Level
• Number of Employees: 5,001-10,000 employees