FPGA Design Engineer (Active Secret Clearance required)

RedBeard Solutions • Reston, VA

19h • Onsite

About The Position

FPGA Design Engineer (Active Secret Clearance required)

Location: Reston VA and Camden NJ, fully onsite (No relocation assistance) Number of openings: 2-4 Benefits: None/Contract Start Date: 2 weeks after offer Clearance Level: Active Secret Schedule: 9/80 (80 hours over 9 days with every other Friday off)

Requirements

• Active Secret Clearance required
• Experience with Xilinx FPGAs and Vivado
• Experience with Revision control system
• 4-6 years of minimum experience with VHDL experience
• Extensive FPGA design going through design and verification process
• Ethernet framing and protocol experience in FPGA (Primarily working on the Ethernet side but if they can demonstrate the PCIe that would suffice) – Looking for the actual interface experience than just the algorithims
• Good written, verbal, and presentation skills
• Strong leader, able to lead design teams
• Bachelor of Science (BS) -Four year degree or Masters (MS) or PhD from an accredited course of study in engineering, engineering technology (chemistry, physics, mathematics, data science, or Electrical/Electronics/Computer Engineering/Computer Science)

Nice To Haves

• Experience with mapping algorithms to architecture
• Experience in C++ (OOP)
• Experience with any of protocols : Ethernet, TCP/IP, PCIe, NVMe, USB
• Experience with Xilinx SoC design with SDKs and PetaLinux OS
• Experience with High-Level Synthesis (HLS) with Vivado HLX or Mentor Catapult
• Experience with Earned Value Management (EVM) – understanding of the schedule, scope, time etc. from an Agile environment

What This Job Offers

• Career Level: Mid Level