FE Engineer

Apple • Cupertino, CA

13h

About The Position

Imagine what you can do here. Apple is a place where extraordinary people gather
to do their lives best work. Together we create products and experiences people
once couldn’t have imagined, and now, can’t imagine living without. It’s the
diversity of those people and their ideas that inspires the innovation that runs
through everything we do.

DESCRIPTION

APPLE INC has the following available in Cupertino, and various unanticipated
locations throughout the USA. RTL design (System Verilog coding) for the digital
logic in Power Management ICs (PMICs). These ICs are mixed signal ICs and
contain a lot of digital control logic. RTL design is the primary responsibility
of a “front-end” engineer in the VLSI design process. RTL simulation and
functional verification of designs using Cadence’s Xcelium and Simvision. All
the designs are simulated, and the waveforms are assessed to verify
functionality. Synthesize RTL designs into ASIC gates and analyze Power,
Performance and Area impact using Synopsys’s Design Compiler or Cadence Genus
synthesis tool. Firmware development using the C language for various processes
in the PMICs including temperature management, SoC voltage and current
monitoring. Script in Perl and Python for ASIC flow development tasks. Run Clock
Domain Crossing simulations for the digital logic in PMICs. Run Reset Domain
Crossing simulations for the digital logic in PMICs. General design signoff
duties; SDC, CDC and other constraints files cleanup. Deliver FPGA build of the
PMICs to facilitate platform emulation with the SoC.. Interact with the Silicon
Validation team to help them understand design, review test plan, and provide
debugging support. Interact with different teams such as Analog Design,
Architecture, DFT and ATE to finalize design specifications and fulfill all
product requirements. 40 hours/week. At Apple, base pay is one part of our total
compensation package and is determined within a range. This provides the
opportunity to progress as you grow and develop within a role. The base pay
range for this role is between $156,853 - $220,900/yr and your base pay will
depend on your skills, qualifications, experience, and location. PAY & BENEFITS:
Apple employees also have the opportunity to become an Apple shareholder through
participation in Apple’s discretionary employee stock programs. Apple employees
are eligible for discretionary restricted stock unit awards, and can purchase
Apple stock at a discount if voluntarily participating in Apple’s Employee Stock
Purchase Plan. You’ll also receive benefits including: Comprehensive medical and
dental coverage, retirement benefits, a range of discounted products and free
services, and for formal education related to advancing your career at Apple,
reimbursement for certain educational expenses — including tuition.
Additionally, this role might be eligible for discretionary bonuses or
commission payments as well as relocation. Learn more about Apple Benefits:
https://www.apple.com/careers/us/benefits.html. Note: Apple benefit,
compensation and employee stock programs are subject to eligibility requirements
and other terms of the applicable plan or program.

Requirements

• Master's degree or foreign equivalent in Electrical and Computer Engineering, Electrical Engineering, Electronics Engineering, or a related field and 2 years of experience in the job offered or related occupation.
• Designing digital logic using SystemVerilog.
• Simulating designs using Cadence or Verilog Simulators.
• Analyzing circuit behavior in Cadence Indago or waveform viewers.
• Synthesizing design into ASIC library gates using Synopsys Design Compiler or Cadence Genus.
• Understanding CDC techniques and ensuring their correct implementation in SV.
• Performing chip tapeout signoff duties, including the review of constraint files and STA reports.
• Running SPICE simulations of circuits for buffer and interconnect delay analysis.
• Doing timing ECOs for design signoff using PrimeTime (PT) DMSA.
• VLSI flow automation using PERL and TCL scripts.
• Running UVM testbenches.

Nice To Haves

• N/A

Responsibilities

• RTL design (System Verilog coding) for the digital logic in Power Management ICs (PMICs).
• RTL simulation and functional verification of designs using Cadence’s Xcelium and Simvision.
• Synthesize RTL designs into ASIC gates and analyze Power, Performance and Area impact using Synopsys’s Design Compiler or Cadence Genus synthesis tool.
• Firmware development using the C language for various processes in the PMICs including temperature management, SoC voltage and current monitoring.
• Script in Perl and Python for ASIC flow development tasks.
• Run Clock Domain Crossing simulations for the digital logic in PMICs.
• Run Reset Domain Crossing simulations for the digital logic in PMICs.
• General design signoff duties; SDC, CDC and other constraints files cleanup.
• Deliver FPGA build of the PMICs to facilitate platform emulation with the SoC.
• Interact with the Silicon Validation team to help them understand design, review test plan, and provide debugging support.
• Interact with different teams such as Analog Design, Architecture, DFT and ATE to finalize design specifications and fulfill all product requirements.

Benefits

• Apple employees also have the opportunity to become an Apple shareholder through participation in Apple’s discretionary employee stock programs.
• Apple employees are eligible for discretionary restricted stock unit awards, and can purchase Apple stock at a discount if voluntarily participating in Apple’s Employee Stock Purchase Plan.
• Comprehensive medical and dental coverage
• Retirement benefits
• A range of discounted products and free services
• For formal education related to advancing your career at Apple, reimbursement for certain educational expenses — including tuition.
• This role might be eligible for discretionary bonuses or commission payments as well as relocation.

What This Job Offers

• Job Type: Full-time
• Career Level: Mid Level