Engineer, ASIC Digital Design

Micron Technology • Minneapolis, MN

3d

About The Position

Design and develop RTL for next-generation DRAM memory controllers and subsystem blocks. Collaborate with full-custom analog design teams and integrate third-party IP and internal SystemVerilog blocks into cohesive digital solutions. Partner multi-functionally with Packaging, Design Verification, Analog Design, Validation, Synthesis, and Physical Design teams to ensure end-to-end design success. Develop HDL models for circuits and participate in analog/digital co-simulation to validate functionality and interfaces. Support chip bring-up and lab validation activities, including hands-on debug and issue resolution. Present technical concepts, design approaches, and implementation details clearly to design peers and multi-functional partners. Learn and utilize AI-enabled tools to improve efficiency and effectiveness within the ASIC design flow.

Requirements

• Bachelor's or Master's degree in Electrical Engineering or a closely related field
• Strong fundamentals in logic design and RTL development using SystemVerilog
• Understanding of verification techniques and high-speed I/O crossings
• Strong written and verbal communication skills, including ability to write and review architectural specifications and RTL
• Experience with software programming and automation, including Linux shell scripting and Python
• Working knowledge of analog and mixed-signal concepts (CMOS/CML logic, PLL, DLL, CDR)
• Collaborative, curious approach with a consistent focus on learning, contributing, and growing

Nice To Haves

• Experience with DRAM interfaces and memory-system RAS concepts (reliability, availability, serviceability)
• Familiarity with industry-standard tools for synthesis, linting, equivalency checking, and formal verification
• Experience participating in chip bring-up and lab validation, including debug and root-cause isolation
• Demonstrated interest in applying AI tools to improve productivity, debug, or design quality within ASIC development flows

Responsibilities

• Design and develop RTL for next-generation DRAM memory controllers and subsystem blocks
• Collaborate with full-custom analog design teams and integrate third-party IP and internal SystemVerilog blocks into cohesive digital solutions
• Partner multi-functionally with Packaging, Design Verification, Analog Design, Validation, Synthesis, and Physical Design teams to ensure end-to-end design success
• Develop HDL models for circuits and participate in analog/digital co-simulation to validate functionality and interfaces
• Support chip bring-up and lab validation activities, including hands-on debug and issue resolution
• Present technical concepts, design approaches, and implementation details clearly to design peers and multi-functional partners
• Learn and utilize AI-enabled tools to improve efficiency and effectiveness within the ASIC design flow

What This Job Offers

• Job Type: Full-time
• Career Level: Mid Level
• Number of Employees: 5,001-10,000 employees