DVT- Technical Lead

Cerebras Systems•Sunnyvale, CA

12h•$175,000 - $275,000•Onsite

About The Position

Cerebras Systems builds the world's largest AI chip, 56 times larger than GPUs. Our novel wafer-scale architecture provides the AI compute power of dozens of GPUs on a single chip, with the programming simplicity of a single device. This approach allows Cerebras to deliver industry-leading training and inference speeds and empowers machine learning users to effortlessly run large-scale ML applications, without the hassle of managing hundreds of GPUs or TPUs. Cerebras' current customers include top model labs, global enterprises, and cutting-edge AI-native startups. OpenAI recently announced a multi-year partnership with Cerebras, to deploy 750 megawatts of scale, transforming key workloads with ultra high-speed inference. Thanks to the groundbreaking wafer-scale architecture, Cerebras Inference offers the fastest Generative AI inference solution in the world, over 10 times faster than GPU-based hyperscale cloud inference services. This order of magnitude increase in speed is transforming the user experience of AI applications, unlocking real-time iteration and increasing intelligence via additional agentic computation. Role Summary We are seeking a hands‑on DVT Technical Lead (Individual Contributor) to own and drive the Design Validation Test (DVT) process end‑to-end across complex electrical engineering boards and full systems. You will define validation strategy, build test plans and infrastructure, lead deep debug and root‑cause analysis (RCA), and drive closure through design changes and re‑test. The domain includes difficult power delivery technology, fast high‑speed I/O, and electro‑mechanical systems with thermal, optics, and high‑power constraints. People management is not required (mentoring is a plus).

Requirements

BS/MS in Electrical or Computer Engineering (or equivalent experience).
8–15+ years of hardware validation/DVT experience on complex board and system-level products.
Demonstrated ownership of board bring‑up and DVT execution: test plan creation, instrumentation, debug, and closure.
Strong background in power delivery validation and measurement (sequencing, margining, droop, ripple/noise, IR drop).
Strong background in high‑speed I/O validation and debug (PCIe/Ethernet‑class links; channel and system-level troubleshooting).
Proficiency with lab equipment: oscilloscopes, logic analyzers, power supplies/analyzers, DC electronic loads; VNAs/BERTs as applicable.
Strong written and verbal communication; ability to present results and drive decisions with data.

Nice To Haves

Experience with rack-scale and/or liquid-cooled systems; validation in environmental chambers.
Experience supporting compliance/safety/EMC efforts as part of DVT readiness.
Python (or similar) for test automation and data analysis; experience integrating results into dashboards/CI workflows.
Experience mentoring engineers/technicians as an informal technical leader.

Responsibilities

Define a risk‑based DVT strategy spanning board/subassembly engineering validation through system integration validation.
Author and maintain DVT plans, procedures, and reports with crisp pass/fail criteria and coverage rationale.
Establish stage gates and readiness reviews for execution quality (fixtures, instrumentation, scripts, SW readiness).
Build and own benchtop and rack-level validation setups that are repeatable and automation‑friendly.
Lead RCA for validation failures; drive corrective actions with design teams; verify fixes through re‑test and data review.
Execute and interpret power integrity/stability measurements (voltage/current stability, droop, ripple/noise, IR drop) and close gaps to requirements.
Validate high‑speed interconnect performance and margin; isolate failures across channel, connector/cable, PHY, and firmware/diagnostics layers.
Partner with diagnostics/software to improve DVT throughput via scripting, logging, and standardized test stages.
Define required data capture and reporting standards to accelerate debug and support release gating.
Drive continual improvements to test coverage, efficiency, and repeatability across builds.
Align EE/ME/FW/Diagnostics/Reliability/Manufacturing on priorities, schedules, and closure criteria.
Influence design-for-testability improvements (debug visibility, margining hooks, instrumentation points, serviceability).