Display Driver IC Engineer

Meta•Sunnyvale, CA

1d•$118,000 - $170,000

About The Position

The Display Systems Team within the VR organization is seeking a Display Driver IC engineer to lead the development of custom product-differentiating pixel pipeline for Meta’s custom driver ICs. In this role, you will be working closely with Display Driver IC (DDIC) architects and DDIC vendors to design, evaluate performance, and embed Meta’s proprietary display IP within the vendor's DDIC for future VR products. This role offers involvement in a mix of forward-looking and product-critical projects, and requires close collaboration with multiple teams within the Meta Reality Labs.

Requirements

Bachelor's degree in Electrical Engineering, Computer Engineering , related fields, or equivalent experience
2+ years of experience working on Display Drivers or equivalent technology
Experience designing pixel pipeline and display IPs
Experience with at least one programming language such as Matlab, Python or C++
Experience communicating complex technical problems both verbally and in writing

Nice To Haves

PhD degree or equivalent experience in the field of Optical Sciences, Optical Engineering, Physics, Electrical Engineering or a similar field
Hands-on experience with FPGA prototyping for display applications
Prior experience with architecture and design of display IP such as sub-pixel rendering, foveation, Mura, burn-in compensation algorithms
Familiar with compression IP design such as DSC

Responsibilities

Define hardware architecture of proprietary display IP for VR displays
Design and implement the algorithm in Verilog with optimized gate-count, meeting performance targets
Collaborate with DDIC vendors to ensure consistency between IP architecture and the DDIC design
Collaborate with vendors to embed IP within the vendor’s DDIC. Supervise chip-level verification
Participate in DDIC design reviews with vendors and assess overall digital design flow including verification coverage, clock synthesis, timing signoff
Collaborate with the system team to bring up and test the algorithm for production readiness