Digital Verification Engineer
About The Position
WaveWorks is seeking a Digital Verification Engineer to join our Core Platform Engineering team. In this role, you will help verify SystemVerilog IP for a wireless SoC using primarily simulation-based verification methodologies. You’ll work closely with design, architecture, and embedded/software teams to drive verification strategy, build robust testbenches, and deliver confidence in complex chip-level behavior. With our unique technology, Waveworks is positioned to meet the needs of a plethora of applications of wireless connectivity that are not well served by conventional wireless solutions. Join us as we work to capture this opportunity and become a significant force in wireless.
Requirements
- BS/MS/PhD in Electrical Engineering, Computer Engineering, Computer Science, or equivalent experience.
- 3+ years of digital verification experience (or equivalent), including verification of non-trivial IP blocks and/or SoCs.
- Strong SystemVerilog skills and comfort reading/debugging RTL.
- Hands-on experience with at least one simulation-based verification methodology: UVM (SystemVerilog class-based verification), and/or cocotb (Python-based verification) or similar framework, with modern verification practices.
- Proficiency debugging simulation issues (waveforms, logs, assertions) and working with common EDA simulators.
- Experience verifying complex systems (multi-clock domains, bus fabrics, interrupts, DMA, low-power states, or similar SoC features).
- Solid scripting ability (Python preferred; bash/tcl a plus) for test automation and tooling.
Nice To Haves
- Verification experience at the SoC/integration level (subsystem assembly, interconnect, register maps, firmware-driven scenarios).
- Experience with AXI/AHB/APB or similar standard on-chip bus protocols.
- Experience with formal verification concepts, SystemVerilog Assertions (SVA), or lint/CDC/RDC tools.
- Familiarity with CI infrastructure for regressions (e.g., GitHub Actions), and managing large regression suites.
- Experience collaborating across design/verification/firmware to reproduce and root-cause silicon-facing issues.
Responsibilities
- Develop and maintain simulation-based verification environments for SystemVerilog RTL (UVM and/or cocotb-based flows).
- Create scalable testbenches, drivers/monitors, scoreboards, reference models, and coverage (functional/code) to validate IP and SoC behavior.
- Build and execute constrained-random and directed tests; debug failures across RTL, testbench, and tool flows.
- Define verification plans, coverage goals, and bring-up strategies in collaboration with design and architecture.
- Drive regressions and continuous integration for verification, including test triage, automation, and reporting.
- Contribute to verification best practices (assertions, checkers, reuse, documentation) across the Core Platform.
Benefits
- Work on verification problems that span from block-level correctness to full-chip integration.
- Help shape verification methodology and infrastructure as the Core Platform grows.
- Join a small team where verification rigor and engineering judgment directly impact tapeout readiness.
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What This Job Offers
Job Type
Full-time
Career Level
Mid Level
Number of Employees
1-10 employees
