DFT Engineer

Broadcom Corporation • San Jose, CA

34d

About The Position

Broadcom's CSG division is seeking candidate for a DFT lead position. The successful candidate will be responsible for leading most complex and cutting edge network switching ASIC DFx (Design for Test/debug & manufacturability) from DFT architecture, to implementation, verification, timing closure, ATE pattern bringup. . You will also drive/push state of the art in the areas of testability, debug and quality, in order to aggressively deliver low DPPM's, while optimizing the cost for test.

Requirements

• Knowledge of Testability techniques and features (SCAN, Built-in-Self-Tests, Loop-Backs etc.) covering digital logic domain, embedded memories and PHY/IO's
• Scan flow development, ATPG pattern generation, verification and coverage analysis
• Experience working with Mentor/Siemens DFT Tessent tool for scan/MBIST/bscan/IJTAG insertion and verification
• Experience working with Cadence DFT tools (Modus and Genus)
• Well versed in JTAG/1500/1687 networks and BSDL, ICL and PDL knowledge
• Strong knowledge of logic & circuit design fundamentals is needed
• Working knowledge of TCL, perl
• Experience in implementation of MBIST for memories and knowledge of repair schemes, algorithms
• Experience in implementation of MBIST for memories and knowledge of repair schemes, algorithms is a must
• Strong Pre/Post Silicon debugging, analytical and independent problem solving ability.
• Must be a team player with good verbal and written communication skills.
• Must be self-driven engineer with good project management and organizational skills to deliver high quality output in a timely manner.
• Experience : Bachelors and 8+ years of related experience

Nice To Haves

• Experience or working knowledge of SERDES, Analog /mixed-signal DFT techniques (like IOBIST, loop-backs etc..) is a plus
• Post Silicon experience in Pattern conversion for Testers, Pattern Bring-up & Debug, Silicon Characterization etc. is a plus
• Experience or familiarity in back-end chip design, Timing, CDC flows is a plus

Responsibilities

• Drive the test quality of the products from Design to Production
• Participate/contribute in silicon bring-up, characterization, and silicon test
• Define and implement various DFx features

Benefits

• Medical, dental and vision plans
• 401(K) participation including company matching
• Employee Stock Purchase Program (ESPP)
• Employee Assistance Program (EAP)
• company paid holidays
• paid sick leave and vacation time

What This Job Offers

• Job Type: Full-time
• Career Level: Mid Level
• Industry: Computer and Electronic Product Manufacturing
• Number of Employees: 5,001-10,000 employees