DFT Engineer (Internship 2026)

Astera Labs Early Career • San Jose, CA

3d

About The Position

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com . As an Astera Labs’ Principal DFT (Design for Test) Engineer Intern, you will be part of the DFT Design team that develops the next generation of Astera Labs’ connectivity products that support the world’s leading cloud service providers and server and networking OEMs. In this role, you have exposure to the full product life cycle, from definition to mass production to end of life of the products. You will be working closely to support all engineering teams, physical design and functions like back-end testing, manufacturing, defect, and reliability analysis. This employee must be team oriented with a focus on solving problems in a collaborative manner between multiple engineering teams.

Requirements

• Working towards B.S. or M.S in Electrical Engineering or related field
• 3.5 GPA or higher
• Self-motivated team worker, good verbal and written communication skills
• Good understanding in VLSI digital design/Layout/Timing closure
• Programming and scripting (Perl, TCL, C++)
• Basic knowledge on circuit design, device delays, and timing at gate-level
• Project work experience using UNIX
• Familiar with industry EDA tools such as Synopsys ICC/FC/Primetime/ICV, Cadence Innovus
• Hardware Design Languages like Verilog, VHDL
• Solid understanding of hierarchical physical design strategies, methodologies and deep sub-micron technology issues

Nice To Haves

• Good understanding in VLSI Design and Digital Design and DV/ Testing
• Programming and scripting (Perl, TCL, C++) and HW design languages like Verilog, VHDL
• Basic knowledge on circuit design, device delays, and timing at gate-level
• Familiarity with industry EDA tools like Synopsys ICC/FC/Primetime/ICV, Cadence Innovus and experience using UNIX
• Solid understanding of hierarchical physical design strategies, methodologies, and deep sub-micron technology issues

Responsibilities

• Support design, test, and manufacturing of connectivity products.
• Gain exposure to the full product lifecycle and collaborate across engineering teams to improve testability, reliability, and production readiness

What This Job Offers

• Career Level: Intern
• Number of Employees: 251-500 employees