Design Verification Lead Engineer

Cadence Systems • Austin, TX

28d

About The Position

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Design Verification Lead Engineer Role Overview: The Lead DV Engineer focuses on the execution and technical management of verification projects. You will lead a focused team to ensure comprehensive test coverage and closure for specific CPU cores or processor blocks.

Requirements

• B.S/M.S in EEE with 5–8+ years of hands-on experience in VLSI design verification.
• Strong command of SystemVerilog Assertions (SVA) , constraint randomization, and UVM.
• Experience with processor integration (e.g., RISC-V or ARM) and industry-standard protocols like AMBA/PCIe.
• Expertise in scripting (Perl, Python, or Tcl) for verification flow automation.

Responsibilities

• Developing and executing detailed verification plans (vPlans) using Cadence vManager.
• Develop UVM scoreboards, monitors, and complex functional coverage models for multi-protocol or processor-specific interfaces.
• Lead the debug of complex RTL failures and coordinate with design engineers to resolve microarchitectural bugs.
• Manage automated regression environments (e.g., Jenkins) and ensure targets for code and functional coverage are met.
• Responsible for technical alignment, project planning, and progress tracking for the verification lifecycle.

What This Job Offers

• Job Type: Full-time
• Number of Employees: 5,001-10,000 employees