Design Verification Engineer

Broadcom • San Jose, CA

11d

About The Position

As a Senior Design Verification Engineer, you will be a key contributor to the functional verification of high-speed Ethernet PCS/MAC/Serdes subsystems and memory controllers. Key Responsibilities Drive the full verification lifecycle, including comprehensive test planning, environment architecture, test execution, and final closure (functional/code coverage). Design and implement scalable, constrained-random UVM environments from scratch. Analyze complex failures involving Ethernet protocols (IEEE 802.3) and physical sublayers, including Gearbox logic, Scramblers, and FEC (Forward error correction). Develop robust SystemVerilog Assertions (SVA) and functional coverage models to validate designs. Partner with Design and Architecture teams to define verification strategies.

Requirements

• Deep expertise in UVM and SystemVerilog.
• Experience verifying Ethernet (10G through 800G+) designs, specifically the PCS/PMA layers.
• Expertise in constrained-random verification and gate-level simulations (GLS)
• Education: Bachelor’s Degree in Electrical/Computer Engineering or a related field.
• Experience: Master’s Degree + 6 years of relevant industry experience; OR Bachelor’s Degree + 8 years of relevant industry experience.

Nice To Haves

• Familiarity with SerDes integration and clock-domain crossing (CDC) in high-speed designs is highly desirable.
• Prior work with High Bandwidth Memory (HBM) or LPDDR memory controllers is beneficial.

Responsibilities

• Drive the full verification lifecycle, including comprehensive test planning, environment architecture, test execution, and final closure (functional/code coverage).
• Design and implement scalable, constrained-random UVM environments from scratch.
• Analyze complex failures involving Ethernet protocols (IEEE 802.3) and physical sublayers, including Gearbox logic, Scramblers, and FEC (Forward error correction).
• Develop robust SystemVerilog Assertions (SVA) and functional coverage models to validate designs.
• Partner with Design and Architecture teams to define verification strategies.

Benefits

• The annual base salary range for this position is $ 120,000 - $192,000 .
• This position is also eligible for a discretionary annual bonus in accordance with relevant plan documents, and equity in accordance with equity plan documents and equity award agreements.
• Broadcom offers a competitive and comprehensive benefits package: Medical, dental and vision plans, 401(K) participation including company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company paid holidays, paid sick leave and vacation time.
• The company follows all applicable laws for Paid Family Leave and other leaves of absence.

What This Job Offers

• Job Type: Full-time
• Career Level: Mid Level
• Number of Employees: 5,001-10,000 employees