Design Verification Engineer - Internal IP
About The Position
Etched is building the world’s first AI inference system purpose-built for transformers - delivering over 10x higher performance and dramatically lower cost and latency than a B200. With Etched ASICs, you can build products that would be impossible with GPUs, like real-time video generation models and extremely deep & parallel chain-of-thought reasoning agents. Backed by hundreds of millions from top-tier investors and staffed by leading engineers, Etched is redefining the infrastructure layer for the fastest growing industry in history. We are seeking a Design Verification Engineer to join our Internal IP DV team. You will ensure the custom IPs powering Sohu — including systolic arrays, DMA engines, and NoCs — are robust, high-performance, and silicon-ready. This role demands creativity, deep technical ability, and the drive to tackle complex verification challenges. You will collaborate with architects, RTL designers, and SW/FW/emulation teams to validate correctness and performance across the full hardware-software stack.
Requirements
- Proficiency with UVM and SystemVerilog.
- Strong debugging and problem-solving skills for complex digital designs.
- Solid knowledge of computer architecture and digital design fundamentals.
- Hands-on experience verifying datapaths, memory systems, interconnects, or high-throughput fabrics.
Nice To Haves
- Familiarity with SystemVerilog Assertions (SVA) and formal verification techniques.
- Experience verifying systolic arrays, DMA engines, or NoC/AXI protocols.
- Scripting skills (Python/Perl/TCL or similar) for automation, debug and regression flows.
Responsibilities
- Develop and maintain UVM/SystemVerilog testbenches for high-performance IPs (compute arrays, DMAs, NoCs, memory subsystems).
- Define and execute verification plans covering functional correctness, corner cases, concurrency, and performance bottlenecks.
- Debug complex datapath and protocol issues in RTL and testbench environments.
- Work closely with architects and designers to validate functionality and design intent.
- Partner with SW, FW, and emulation teams to ensure end-to-end bring-up and debug coverage.
- Contribute to reusable DV infrastructure, coverage models, and methodology improvements.
Benefits
- Medical, dental, and vision packages with generous premium coverage
- $500 per month credit for waiving medical benefits
- Housing subsidy of $2k per month for those living within walking distance of the office
- Relocation support for those moving to San Jose (Santana Row)
- Various wellness benefits covering fitness, mental health, and more
- Daily lunch + dinner in our office
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What This Job Offers
Job Type
Full-time
Career Level
Mid Level
Education Level
No Education Listed
