Design Verification Engineer Intern
About The Position
Cadence Silicon Realization Group is hiring students to join their services teams in San Jose. This engineering intern opportunity is with a world leader in computational software, semiconductor design IP, and system verification hardware. Cadence's customers are innovative companies delivering electronic products for dynamic market applications including hyperscale computing, 5G communications, automotive, mobile, aerospace, consumer, industrial, and healthcare. The Design Verification Engineer Intern will join the Silicon Realization Group (SRG) and work closely with Verification engineers to verify digital designs for correctness, performance, and functionality. Responsibilities include developing and executing verification testbenches, debugging simulation failures, and contributing to high-quality silicon delivery. Cadence is a global electronic design automation company providing software, hardware, and intellectual property to design advanced semiconductor chips, recognized by Fortune Magazine as one of the 100 Best Companies to Work For.
Requirements
- Currently pursuing a BS/MS in Electrical Engineering, Computer Engineering, or related field
- Strong understanding of digital design fundamentals and RTL concepts
- Working knowledge of Verilog/SystemVerilog
- Familiarity with EDA simulation tools
- Good analytical, communication, and teamwork skills
Nice To Haves
- UVM knowledge
- Python/Perl scripting
Responsibilities
- Develop and maintain verification environments using SystemVerilog/UVM
- Write and execute test cases to validate RTL functionality
- Debug design and verification issues using simulation and waveform analysis
- Collaborate with design teams to review specifications and verification plans
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What This Job Offers
Career Level
Intern
Number of Employees
5,001-10,000 employees
