Design Verification Engineer III

Arrow Electronics•Mountain View, CA

19h•Onsite

About The Position

What You'll Be Doing: Candidate roles and responsibilities: Responsible for analyzing and capturing requirements, Functional Testplan development, Verification plan development related to Consumer Electronics and AI ASICs, Mixed Signal ASICs Responsible to create reusable verification environment in System Verilog, UVM (Universal Verification Methodology) based on the strategy using Ethernet UVM VIPs and models. Verification environment include creating testbench, integrating DUT (Design under Test) with testbench, integrating the third-party VIP (Verification Intellectual Property), creating verification components such as drivers, monitors, checkers etc, integrating the created IUVCs (Interface UVM Components) in testbench. Complex corner case scenarios development for thorough verification Responsible for signing off on the throughput and BW analysis of end-to-end Traffic at SoC level Thorough analysis of Functional and Code coverage and getting it to 100%. What We Are Looking For: Analyse the system architecture of advanced optical networking devices and architected the verification strategy to ensure all functional blocks met system-level requirements and IEEE Ethernet standards. • Performed constraint-random verification of high-speed networking DSP chips using eInfochips’ Ethernet and Optical Transport Layer (OTL) Verification IPs, covering data rates from 10 Gbps to 400 Gbps, including advanced 200G and 400G devices compliant with IEEE 802.3 standards. • Support plug-and-play switches by validating complex modulation schemes using enhanced Ethernet and Optical Transport Layer (OTL) Verification IP (VIP) capabilities for upcoming networking devices. Skills: Optical Internetworking protocols IEEE Ethernet standards 200Gbps SerDes Interface Ethernet and OTL Verification IPs Pre-silicon verification tools and techniques Development of reusable verification components including test suites, assertions, protocol checks, and functional coverage models What’s In It for You: At Arrow, we recognize that financial rewards and great benefits are important aspects of an ideal job. That’s why we offer competitive financial compensation, including various compensation plans and a solid benefits package. Medical, Dental, Vision Insurance 401k, With Matching Contributions Short-Term/Long-Term Disability Insurance Health Savings Account (HSA)/Health Reimbursement Account (HRA) Options Paid Time Off (including sick, holiday, vacation, etc.)Tuition Reimbursement Growth Opportunities And more!

Requirements

Analyse the system architecture of advanced optical networking devices and architected the verification strategy to ensure all functional blocks met system-level requirements and IEEE Ethernet standards.
Performed constraint-random verification of high-speed networking DSP chips using eInfochips’ Ethernet and Optical Transport Layer (OTL) Verification IPs, covering data rates from 10 Gbps to 400 Gbps, including advanced 200G and 400G devices compliant with IEEE 802.3 standards.
Support plug-and-play switches by validating complex modulation schemes using enhanced Ethernet and Optical Transport Layer (OTL) Verification IP (VIP) capabilities for upcoming networking devices.
Optical Internetworking protocols
IEEE Ethernet standards
200Gbps SerDes Interface
Ethernet and OTL Verification IPs
Pre-silicon verification tools and techniques
Development of reusable verification components including test suites, assertions, protocol checks, and functional coverage models

Responsibilities

Analyzing and capturing requirements
Functional Testplan development
Verification plan development related to Consumer Electronics and AI ASICs, Mixed Signal ASICs
Create reusable verification environment in System Verilog, UVM (Universal Verification Methodology) based on the strategy using Ethernet UVM VIPs and models
Create testbench, integrating DUT (Design under Test) with testbench, integrating the third-party VIP (Verification Intellectual Property), creating verification components such as drivers, monitors, checkers etc, integrating the created IUVCs (Interface UVM Components) in testbench
Complex corner case scenarios development for thorough verification
Signing off on the throughput and BW analysis of end-to-end Traffic at SoC level
Thorough analysis of Functional and Code coverage and getting it to 100%