Design Verification Engineer III

Arrow Electronics•Mountain View, CA

14h•Onsite

About The Position

What You'll Be Doing: Candidate roles and responsibilities: Responsible for analyzing and capturing requirements, Functional Testplan development, Verification plan development related to Consumer Electronics and AI ASICs, Mixed Signal ASICs Responsible to create reusable verification environment in System Verilog, UVM (Universal Verification Methodology) based on the strategy using Ethernet UVM VIPs and models. Verification environment include creating testbench, integrating DUT (Design under Test) with testbench, integrating the third-party VIP (Verification Intellectual Property), creating verification components such as drivers, monitors, checkers etc, integrating the created IUVCs (Interface UVM Components) in testbench. Complex corner case scenarios development for thorough verification Responsible for signing off on the throughput and BW analysis of end-to-end Traffic at SoC level Thorough analysis of Functional and Code coverage and getting it to 100%. What We Are Looking For: Analyse the system architecture of advanced optical networking devices and architected the verification strategy to ensure all functional blocks met system-level requirements and IEEE Ethernet standards. • Performed constraint-random verification of high-speed networking DSP chips using eInfochips’ Ethernet and Optical Transport Layer (OTL) Verification IPs, covering data rates from 10 Gbps to 400 Gbps, including advanced 200G and 400G devices compliant with IEEE 802.3 standards. • Support plug-and-play switches by validating complex modulation schemes using enhanced Ethernet and Optical Transport Layer (OTL) Verification IP (VIP) capabilities for upcoming networking devices. What’s In It for You: At Arrow, we recognize that financial rewards and great benefits are important aspects of an ideal job. That’s why we offer competitive financial compensation, including various compensation plans and a solid benefits package. About eInfochips: eInfochips, an Arrow company (Fortune #154), is a leading global provider of product engineering and semiconductor design services. A rich history of over two decades, with over 500+ products developed and 40M deployments in 140 countries, eInfochips continues to fuel technological innovations in multiple verticals. eInfochips has strategic technology partnerships with Qualcomm, NVIDIA, NXP, Analog Devices, Texas Instruments, Amazon, Microsoft and Google to name a few. Along with Arrow’s $33B in revenues, 22,000 employees, and 345 locations serving over 80 countries, eInfochips is primed to accelerate connected products innovation for 150,000+ global clients. eInfochips acts as a catalyst to Arrow’s Sensor-to-Sunset initiative and offers complete edge-to-cloud capabilities for its clients. Please visit www.einfochips.com for our portfolio of product engineering services across various industries & verticals. EEO Statement: Arrow is an equal opportunity employer. All applicants will be considered for employment without attention to race, color, religion, gender, age, sexual orientation, gender identity, national origin, veteran or disability status. (Arrow EEO/AAP policy) We anticipate this requisition will be open for a minimum of five days, though it may be open for a longer period of time. We encourage your prompt application. In any materials you submit, you may redact or remove age-identifying information such as age, date of birth, or dates of school attendance or graduation. You will not be penalized for redacting or removing this information.

Requirements

Optical Internetworking protocols
IEEE Ethernet standards
200Gbps SerDes Interface
Ethernet and OTL Verification IPs
Pre-silicon verification tools and techniques
Development of reusable verification components including test suites, assertions, protocol checks, and functional coverage models

Responsibilities

Responsible for analyzing and capturing requirements
Functional Testplan development
Verification plan development related to Consumer Electronics and AI ASICs, Mixed Signal ASICs
Responsible to create reusable verification environment in System Verilog, UVM (Universal Verification Methodology) based on the strategy using Ethernet UVM VIPs and models
Verification environment include creating testbench, integrating DUT (Design under Test) with testbench, integrating the third-party VIP (Verification Intellectual Property), creating verification components such as drivers, monitors, checkers etc, integrating the created IUVCs (Interface UVM Components) in testbench
Complex corner case scenarios development for thorough verification
Responsible for signing off on the throughput and BW analysis of end-to-end Traffic at SoC level
Thorough analysis of Functional and Code coverage and getting it to 100%