Candidate would be required to work on Design Implementation activities related to complex digital and mixed signal IP blocks used in the development of Broadcom's ASIC / SoC products. Activities include constraints development, constraints verification, deployment of SDF, extracted timing models and timing closure. Additionally, the candidate could be required to do block-level synthesis, verification (static, formal) and place and route related activities. Candidate will work closely with the IP and SOC design teams to enable block and ASIC level timing closure. The engineer will work with the internal ASIC / SoC teams and Broadcom customers to support constraints, timing analysis, timing closure, and physical implementation involving the IP blocks. Developing SDF's and ETM's for various IP blocks. Debugging customer problems involving the use of these IP deliverables. Will be exposed to various IP and ASIC / SoC developments. Opportunities for customer interaction and other high profile activities are available to members of this team. In this role, the candidate will apply Broadcom's proven design methodology and milestone flow to meet Broadcom's rigorous criteria for achieving Right-first time silicon.
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Job Type
Full-time
Career Level
Mid Level
Industry
Computer and Electronic Product Manufacturing
Number of Employees
5,001-10,000 employees