Design Implementation Engineer

Broadcom • San Jose, CA

8d

About The Position

Responsibilities Include: Work on Design Implementation activities related to place and route and/ or timing closure – floor-planning, partitioning, placement, clock tree synthesis, route, timing analysis, timing closure, physical verification (LVS/DRC). Drive tools and methodologies to achieve desired PPA metrics. Complete equivalence checks, STA, Timing closure and power optimization. Implement timing and functional ECOs. Apply Broadcom's proven design methodology and milestone flow to meet Broadcom's rigorous criteria for achieving Right-first time silicon.

Requirements

• Primary expertise in place and route and/or timing (constraints, STA) can be considered for this position.
• Proficient in design implementation activities both at block and SoC level.
• Well experienced in floor-planning, partitioning, placement, clock tree synthesis, route and physical verification and/ or constraints development, constraints validation, timing analysis and closure.
• Experience with formal verification, timing analysis and Eco implementation.
• Experience with tools such as Primetime, ICC2, Innovus, Caliber, LEC, PrimeTime etc is highly desirable.
• Full chip tapeout experience based on 7nm and lower technologies is highly preferred.
• Hands on experience with timing analysis and place and route tools for ASIC/ SoC Design is a must.
• Good problem solver.
• Self starter who can work independently.
• Experienced in working in a global team and dynamic environment.
• Possess ability to learn and adapt to new tools and methodologies on the fly.
• Excellent communication skills.
• BS in Electrical Engineering/ Computer Engineering or related field and 12+ years of related experience; or an MS in Electrical Engineering/ Computer Engineering or related field and 10+ years of related experience.

Responsibilities

• Work on Design Implementation activities related to place and route and/ or timing closure – floor-planning, partitioning, placement, clock tree synthesis, route, timing analysis, timing closure, physical verification (LVS/DRC).
• Drive tools and methodologies to achieve desired PPA metrics.
• Complete equivalence checks, STA, Timing closure and power optimization.
• Implement timing and functional ECOs.
• Apply Broadcom's proven design methodology and milestone flow to meet Broadcom's rigorous criteria for achieving Right-first time silicon.

Benefits

• Medical, dental and vision plans
• 401(K) participation including company matching
• Employee Stock Purchase Program (ESPP)
• Employee Assistance Program (EAP)
• company paid holidays
• paid sick leave and vacation time.

What This Job Offers

• Job Type: Full-time
• Career Level: Mid Level
• Number of Employees: 5,001-10,000 employees