Design Engineering Manager, Texas Institute for Electronics

The University of Texas at Austin•Austin, TX

13d•Onsite

About The Position

The Design Engineering Manager will supervise a team of Design Engineers who will design and develop innovative semiconductor circuits and test structures to support TIE's facility manufacturing highly reliable and leading-edge 2.5D and 3D packaging solutions. This position will also manage and support multi-material (Silicon, III-V, Glass) and multi-domain (Analog/Digital, RF, Power, Thermal, Mechanical Stress, Signal Integrity) design, modeling, and production activities.

Requirements

Bachelor's degree in Electrical Engineering, Semiconductor Physics, Materials Science, or a related field
10+ years of relevant industry experience in semiconductor IC design
Previous supervisory experience with small to medium-sized teams
Strong understanding of semiconductor device physics and mixed signal circuit design
Excellent problem-solving skills and attention to detail
Strong communication and teamwork skills
Ability to manage multiple projects in a fast-paced environment
Proficiency in industry-standard EDA software for circuit and/or package design
Relevant education and experience may be substituted as appropriate.

Nice To Haves

Master's or higher degree in relevant semiconductor engineering fields
Experience with 2.5D and 3D semiconductor packaging technologies
Solid understanding of various packaging technologies (wire bonding, flip-chip, wafer-level packaging)
Strong background in DFT/DFM methodologies and BIST techniques
Experience in multi-physics modeling (Power, Thermal, Mechanical, Signal Integrity, RF)
Experience in a startup or R&D environment

Responsibilities

Supervise, guide, direct, and help train team of TIE Design Engineers through hands-on collaboration. Assist with hiring, performance reviews, and upper management communication on product status and roadmap alignment
Design and develop mixed signal circuits, test vehicles, test chips, and test structures for TIE's 3D-ADK (Assembly Design Kit).
Develop workflows, 2.5D/3D modeling methods, and standard cells for multi-chiplet, heterogeneous micro-systems.
Collaborate with Product and Test engineering teams to ensure performance, yield, reliability, and BIST methodologies.
Work with EDA vendors to evaluate and improve tool offerings and capabilities.
Develop and implement advanced models for semiconductor packaging effects.
Improve automation of circuits and layouts using scripting languages.
Participate in industry 'design standards' workshops and consortiums.
Collaborate with internal and external design teams on package compatibility.
Design and execute experiments for packaging performance optimization.
Conduct multi-physics modeling and simulation studies.
Stay current with industry trends and emerging technologies.
Other related functions as assigned.

Benefits

Competitive health benefits (employee premiums covered at 100%, family premiums at 50%)
Voluntary Vision, Dental, Life, and Disability insurance options
Generous paid vacation, sick time, and holidays
Teachers Retirement System of Texas, a defined benefit retirement plan, with 8.25% employer matching funds
Additional Voluntary Retirement Programs: Tax Sheltered Annuity 403(b) and a Deferred Compensation program 457(b)
Flexible spending account options for medical and childcare expenses
Robust free training access through LinkedIn Learning plus professional conference opportunities
Tuition assistance
Expansive employee discount program including athletic tickets
Free access to UT Austin's libraries and museums with staff ID card
Free rides on all UT Shuttle and Austin CapMetro buses with staff ID card