Design Aids & Automation Engineering Professional

Computer Task Group, Inc

19h•$85,000 - $95,000•Remote

About The Position

CTG is seeking to fill a Design Aids & Automation Engineering Professional position for our client. Location: Remote Duration: Ongoing Contract Duties: Develop test structure layouts using design automation per specified requirements, utilizing industry-standard EDA tools including the Cadence Virtuoso Design Environment and SKILL programming. Create manual layout cells based on defined specifications using the Cadence Virtuoso Design Environment. Develop parameterized cells (p-cells) to support layout automation and reusable design components. Interpret and apply design rules and macro specifications to ensure layout intent is met. Ensure all layouts successfully pass Design Rule Checks (DRC). Collaborate closely with process development engineers, test structure designers, and layout technicians to deliver high-quality design enablement solutions. Debug and resolve layout and automation issues in a collaborative, team-oriented environment. Focus primarily on test structure layouts rather than functional circuitry designs. Skills: Strong experience with the Cadence Virtuoso layout design tool (3+ years). Experience with Cadence SKILL programming language (2+ years). Solid understanding of physical layout concepts, technology ground rules, and semiconductor manufacturing processes. Proven ability to debug errors and solve complex technical problems. Strong teamwork and collaboration skills. Fluent verbal and written English communication skills. Preferred: Experience with advanced sub-micron semiconductor technology nodes. Preferred: Experience using Synopsys ICV for DRC checking. Preferred: Advanced SKILL programming experience for p-cell development and design automation. Experience: Minimum of 3 years of hands-on experience in semiconductor physical layout and design automation. Prior experience developing test structures or similar non-functional layout designs is strongly preferred. Education: Bachelor’s degree in Electrical Engineering, Computer Engineering, Materials Science, or a related technical discipline, or equivalent professional experience. Excellent verbal and written English communication skills and the ability to interact professionally with a diverse group are required. CTG does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services for this role. To Apply: To be considered, please apply directly to this requisition using the link provided. For additional information, please contact Tana Stilloe at [email protected]. Kindly forward this to any other interested parties. Thank you! The expected base salary for this position ranges from $85,000 to $95,000. Salary offers are based on a wide range of factors including relevant skills, training, experience, education, market factors, and where applicable, licensure or certifications obtained. In addition to salary, a competitive benefit package is also offered. About CTG CTG, a Cegeka company, delivers IT and business solutions that enhance clients’ digital agility, empowering them to seize new opportunities and overcome any challenge. Backed by more than 60 years’ experience and a commitment to being a reliable, results-driven partner, we work shoulder to shoulder with clients to shape digital together. Our vision is to be an indispensable partner to our clients and the preferred career destination for digital and technology experts. With more than 9,000 team members in over 15 countries, we combine global expertise with local insight to deliver innovative solutions. We operate across the Americas, Europe, and India, working with over 3,000 clients in many of today's highest-growth industries. Together, we shape what’s next—working shoulder to shoulder to deliver impactful solutions for our clients and society. Our culture is built by the people who work at CTG, the values we hold, and the actions we take. It's a living, breathing thing that is renewed every day through the ways we engage with each other, our clients, and our communities. At CTG, you’ll find a workplace where you are encouraged to grow, supported in your ambitions, and empowered to shape your own career journey. For more information, visit www.ctg.com. CTG will consider for employment all qualified applicants including those with criminal histories in a manner consistent with the requirements of all applicable local, state, and federal laws. CTG is an Equal Opportunity Employer. CTG will assure equal opportunity and consideration to all applicants and employees in recruitment, selection, placement, training, benefits, compensation, promotion, transfer, and release of individuals without regard to race, creed, religion, color, national origin, sex, sexual orientation, gender identity and gender expression, age, disability, marital or veteran status, citizenship status, or any other discriminatory factors as required by law. CTG is fully committed to promoting employment opportunities for members of protected classes.

Requirements

Strong experience with the Cadence Virtuoso layout design tool (3+ years).
Experience with Cadence SKILL programming language (2+ years).
Solid understanding of physical layout concepts, technology ground rules, and semiconductor manufacturing processes.
Proven ability to debug errors and solve complex technical problems.
Strong teamwork and collaboration skills.
Fluent verbal and written English communication skills.
Minimum of 3 years of hands-on experience in semiconductor physical layout and design automation.
Excellent verbal and written English communication skills and the ability to interact professionally with a diverse group are required.

Nice To Haves

Experience with advanced sub-micron semiconductor technology nodes.
Experience using Synopsys ICV for DRC checking.
Advanced SKILL programming experience for p-cell development and design automation.
Prior experience developing test structures or similar non-functional layout designs is strongly preferred.

Responsibilities

Develop test structure layouts using design automation per specified requirements, utilizing industry-standard EDA tools including the Cadence Virtuoso Design Environment and SKILL programming.
Create manual layout cells based on defined specifications using the Cadence Virtuoso Design Environment.
Develop parameterized cells (p-cells) to support layout automation and reusable design components.
Interpret and apply design rules and macro specifications to ensure layout intent is met.
Ensure all layouts successfully pass Design Rule Checks (DRC).
Collaborate closely with process development engineers, test structure designers, and layout technicians to deliver high-quality design enablement solutions.
Debug and resolve layout and automation issues in a collaborative, team-oriented environment.
Focus primarily on test structure layouts rather than functional circuitry designs.