CPU Design Intern
About The Position
About SiFive As the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most data-intensive applications in the world. SiFive’s unrivaled compute platforms have enabled leading technology companies around the world to innovate, optimize, and deliver the most advanced solutions of tomorrow across every market segment of chip design, including artificial intelligence, machine learning, automotive, datacenter, mobile, and consumer. With SiFive, the future of RISC-V has no limits. As an Intern on the Out-of-Order Core/Cache Design team, you will develop RTL for SiFive’s flagship RISC-V core series using the Chisel hardware description language. Specific projects will depend on the interests of the candidate, but may include RTL feasibility experiments, power analysis/reduction, performance enhancements, and/or designing/improving small logic modules.
Requirements
- Pursuing a Master's or PhD in Computer Engineering, Computer Science, Electrical Engineering, or a similar discipline.
- Familiarity or academic experience with Chisel, or at least Object Oriented Programming or functional programming, is strongly preferred.
- Advanced academic understanding of Computer Architecture, Out-of-Order CPU Micro-architecture, Caches, and RTL design.
Benefits
- healthcare and retirement plans
- paid time off
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What This Job Offers
Career Level
Intern
Number of Employees
251-500 employees
